US3859595A
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Method for measuring traps in semiconductors
Assignee: AT&T Inc
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Filing: 1973-12-06
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Granted: 1975-01-07
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Expires: 1993-12-06
Abstract
Abstract In order to measure the trap concentration in the neighborhood of a P-N junction in a semiconductor body, the junction is subjected to a reverse bias voltage upon which is superimposed a positive-going voltage pulse (reducing the bias voltage) sufficient to saturate the traps. After the pulse has terminated, the transient RF capacitance response of the body is measured at two predetermined times; and an electrical signal representative of the difference in the capacitance is then generated. The profile of this difference in capacitance as a function of temperature of the semiconductor body yields the relative concentration of traps as well as their activation energies in the semiconductor.
Inventors
- 👤 David Vern Lang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:02
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/26; G01R31/2648; G01R31/28; G01R31/282; G01R31/2831
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
125 words
A method for testing a semiconductor body containing a P-N junction which comprises the steps of: a. maintaining the P-N junction under a reverse bias voltage at a first temperature through steps (b) through (d); b. applying a voltage pulse across the P-N junction in the body superimposed on the reversed bias voltage; c. developing a first signal proportional to the transient RF capacitance of the junction in the body during a first predetermined time interval after cessation of the pulse; d. developing a second signal proportional to the transient RF capacitance of the junction in the body during a second predetermined time interval after cessation of the pulse; and e. developing a third signal proportional to the difference between the first and second signals.
Claim 2
Independent Claim
125 words
A method for testing a semiconductor body containing a P-N junction which comprises the steps of: a. maintaining the P-N junction under a reverse bias voltage at a first temperature through steps (b) through (d); b. applying a voltage pulse across the P-N junction in the body superimposed on the reversed bias voltage; c. developing a first signal proportional to the transient RF capacitance of the junction in the body during a first predetermined time interval after cessation of the pulse; d. developing a second signal proportional to the transient RF capacitance of the junction in the body during a second predetermined time interval after cessation of the pulse; and e. developing a third signal proportional to the difference between the first and second signals.
Claim 3
Dependent Claim
41 words
The steps recited in claim 1 followed by a repetition of suCh steps but with the first temperature being changed to a second temperature which is substantially different from the first temperature, all other control parameters being kept substantially the same.
Claim 4
Dependent Claim
38 words
The steps recited in claim 2 followed by another repetition of the steps recited in claim 1 with the first temperature being changed to a third temperature which is substantially different from the first and the second temperatures.
Claim 5
Independent Claim
105 words
A method for testing a semiconductor body containing an electrical barrier under a reverse electrical bias which comprises the steps of: a. maintaining the body substantially at a given temperature during steps (a) through (c); b. applying an electrical pulse to the body superimposed on the bias; c. sampling a transient response of the barrier during a first sample time interval after cessation of the pulse and developing an electrical signal representative of the time-averaged transient response of the barrier during the first sample time interval; d. repeating steps (a) through (c) at a different temperature, all other control parameters being kept substantially the same.
Claim 6
Independent Claim
105 words
A method for testing a semiconductor body containing an electrical barrier under a reverse electrical bias which comprises the steps of: a. maintaining the body substantially at a given temperature during steps (a) through (c); b. applying an electrical pulse to the body superimposed on the bias; c. sampling a transient response of the barrier during a first sample time interval after cessation of the pulse and developing an electrical signal representative of the time-averaged transient response of the barrier during the first sample time interval; d. repeating steps (a) through (c) at a different temperature, all other control parameters being kept substantially the same.
Claim 7
Dependent Claim
47 words
A method for testing a body in accordance with claim 4 in which the body is a semiconductor containing a P-N junction under a reverse bias voltage upon which the electrical pulse is superimposed, the transient response being the RF capacitance of the body across the junction.
Claim 8
Dependent Claim
33 words
A method for testing a body in accordance with claim 5 in which the transient response is the difference between the RF capacitance during two disjoint time intervals after cessation of the pulse.
Claim 9
Dependent Claim
30 words
A method for testing a body in accordance with claim 6 in which the semiconductor is gallium phosphide containing zinc and oxygen impurities which produce traps in the gallium phosphide.
Claim 10
Independent Claim
136 words
A method for testing a semiconductor body for traps, the body containing a P-N junction with the traps in the neighborhood of the junction which comprises the steps of: a. maintaining the neighborhood of the junction substantially at a first temperature during steps (b) through (c) and subjecting the body to a reverse voltage bias during steps (b) through (d); b. applying a voltage pulse to the body (superimposed on the bias) sufficient to saturate the traps with charge carriers; c. developing an electrical signal representative of the difference C(t1) - C(t2) of the transient RF capacitance of the body during two disjoint predetermined time intervals t1 and t2 after cessation of the pulse; d. repeating steps (b) and (c) while maintaining the neighborhood of the junction substantially at a second temperature different from the first.
Claim 11
Independent Claim
136 words
A method for testing a semiconductor body for traps, the body containing a P-N junction with the traps in the neighborhood of the junction which comprises the steps of: a. maintaining the neighborhood of the junction substantially at a first temperature during steps (b) through (c) and subjecting the body to a reverse voltage bias during steps (b) through (d); b. applying a voltage pulse to the body (superimposed on the bias) sufficient to saturate the traps with charge carriers; c. developing an electrical signal representative of the difference C(t1) - C(t2) of the transient RF capacitance of the body during two disjoint predetermined time intervals t1 and t2 after cessation of the pulse; d. repeating steps (b) and (c) while maintaining the neighborhood of the junction substantially at a second temperature different from the first.
Claim 12
Dependent Claim
13 words
The method recited in claim 8 in which the semiconductor is gallium phosphide.
Claim 13
Dependent Claim
12 words
The method of claim 8 in which the traps include zinc-oxygen pairs.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-01-06 | 1978-07-08 | 1979-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-01-06 | 1982-07-08 | 1983-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-01-06 | 1986-07-08 | 1987-01-07 | $7700.00 | Window Closed / Lapsed |