Sequencing timers

Claim 2

A sequencing timer having a plurality of sequences all starting at the same time and produces a pulse at the end of each sequence, consists of: a d-c power source, having a positive and a negative terminal, said negative terminal is connected to a common lead, said positive terminal is connected to the first terminal of a power switch, while the second terminal of said power switch is connected to a supply lead, a clock frequency source includes a timing resistor connected between said supply lead and a first terminal of a current limiting resistor whose second terminal is connected to the first plate of a storage capacitor having the second plate connected to said common lead, interconnection of said current limiting resistor and said storage capacitor is connected to the anode electrode of a Programmable Unijunction Transistor (PUT) whose cathode electrode is connected through a pulse forming resistor to said common lead, gate electrode of said PUT is connected through a biasing resistor to said common lead, said interconnection of gate electrode and biasing resistor is connected also to the cathode electrode of a compensating diode having anode electrode connected to interconnection of two PUT reference voltage resistors connected between said common and said supply lead, said PUT cathode electrode is connected to a pulse stretching circuit which includes anode electrode of a blocking diode whose cathode electrode is connected to the first plate of a capacitor, having the second plate connected to said common lead, a base resistor connected between the said diode-capacitor interconnection and a base electrode of an n-p-n transistor having emitter electrode connected to said common lead and the collector electrode connected through a relay coil to said supply lead, a transient protection diode is connected across said relay coil having cathode electrode connected to the positive end of said coil, said relay coil operating multiple sets of mutually isolated contacts, each set of contacts is utilized to pulse at least one sequencing circuit which includes a normally open contact connected through a timing resistor to said supply lead, a common contact being connected through a current limiting resistor to the interconnection of the first plate of a storage capacitor, having second plate connected to said common lead, and an anode electrode of a PUT, whose cathode electrode is connected to an output terminal and to the first terminal of a cathode resistor, having second terminal connected to said common lead, the gate electrode of said PUT is connected through a biasing resistor to said common lead and to the cathode electrode of a biasing diode, whose anode electrode is connected to the interconnection of the two PUT reference voltage resistors connected between said common and said supply lead.

Claim 3

Circuit as recited in claim 1 and having said timing resistor adjustable to provide varying of the clock frequency thus, duration of all sequence intervals.

Claim 4

Circuit as recited in claim 1 and having said timing resistor adjustable, within said sequencing circuit, to provide independently adjustable intervals in each and every sequence.

Claim 5

Circuit as recited in claim 1 and having one single sequence by provision of a single set of contacts and a single sequencing circuit.

Claim 6

A sequencing timer having the plurality of sequences, the first sequence starting at the moment the power is supplied to the circuitry, the second sequence starting at the end of the first sequence, the nth sequence starting at the end of n - 1st sequence, a pulse is produced at the end of each sequence, said sequencing timer consisting of: a d-c power source, having a positive and a negative terminal, said negative terminal is connected to a common lead, sAid positive terminal is connected to the first terminal of a power switch, while the second terminal of said power switch is connected to a supply lead, a clock frequency source includes a timing resistor connected between said supply lead and a first terminal of a current limiting resistor whose second terminal is connected to the first plate of a storage capacitor having the second plate connected to said common lead, interconnection of said current limiting resistor and said storage capacitor is connected to the anode electrode of a Programmable Unijunction Transistor (PUT) whose cathode electrode is connected through a pulse forming resistor to said common lead, gate electrode of said PUT is connected through a biasing resistor to said common lead, said interconnection of gate electrode and biasing resistor is connected also to the cathode electrode of a compensating diode having anode electrode connected to interconnection of two PUT reference voltage resistors connected between said common and said supply lead, said PUT cathode electrode is connected to a pulse stretching circuit which includes anode electrode of a blocking diode whose cathode electrode is connected to the first plate of a capacitor, having the second plate connected to said common lead, a base resistor connected between the said diode-capacitor interconnection and a base electrode of an n-p-n transistor having emitter electrode connected to said common lead and the collector electrode connected through a relay coil to said supply lead, a transient protection diode is connected across said relay coil having cathode electrode connected to the positive end of said coil, said relay coil operating multiple sets of mutually isolated contacts, each set of contacts is utilized to pulse at least one sequencing circuit, the first set of contacts is utilized to pulse the first sequencing circuit which includes a normally open contact connected through a timing resistor to said supply lead, a common contact being connected through a current limiting resistor to the interconnection of the first plate of a storage capacitor, having second plate connected to said common lead, and an anode electrode of a PUT, whose cathode electrode is connected to an output terminal and to the first terminal of a cathode resistor, having second terminal connected to said common lead, the gate electrode of said PUT is connected through a biasing resistor to said common lead and to the cathode electrode of a biasing diode, whose anode electrode is connected to the interconnection of the two PUT reference voltage resistors connected between said common and said supply lead, the first sequence output terminal is also connected to the gate electrode of the first Silicon Controlled Rectifier (SCR) having the cathode electrode connected to said common lead and anode electrode connected through a first anode resistor to said supply lead, said anode electrode is also connected through a first base resistor to the base electrode of a first p-n-p transistor whose emitter electrode is connected to said supply lead and, collector electrode connected to the next sequencing circuit thus acts as the first supply lead, a second set of contacts which consists of a normally open contact and a common contact, these contacts being used to pulse a second sequencing circuit, which is of identical configuration as described first sequencing circuit, said second set of contacts operates associated circuit after the first sequencing time interval is over, said second sequence circuit being able to deliver a pulse at the end of said second sequence interval, and supply the power to the third sequencing circuit, an nth set of contacts which consists of a normally open contact and a common contact, these contacts are used to pulse the nth sequencing circuit, n being an integer larger than two, normally open contact is connEcted to the first terminal of the nth timing resistor whose second terminal is connected to the collector electrode of n - 1st sequencing circuit, said collector electrode acting as the n-1st supply lead, the common contact is connected through the nth limiting resistor to the first plate of an nth storage capacitor which has the second plate connected to said common lead, said first plate is also connected to the anode electrode of the nth PUT having cathode electrode connected through the nth cathode resistor to said common lead, said cathode is also connected to an nth output terminal, gate electrode of said nth PUT is connected through an nth biasing resistor to said common lead, said interconnection of biasing resistor and gate electrode is connected also to the cathode electrode of an nth compensating diode whose anode electrode is connected to the interconnection of the two nth PUT reference voltage resistors connected between said common and said n - 1st supply lead, said nth sequence circuit being able to produce a pulse at the end of the nth sequence interval.

Claim 7

A sequencing timer having the plurality of sequences, the first sequence starting at the moment the power is supplied to the circuitry, the second sequence starting at the end of the first sequence, the nth sequence starting at the end of n - 1st sequence, a pulse is produced at the end of each sequence, said sequencing timer consisting of: a d-c power source, having a positive and a negative terminal, said negative terminal is connected to a common lead, sAid positive terminal is connected to the first terminal of a power switch, while the second terminal of said power switch is connected to a supply lead, a clock frequency source includes a timing resistor connected between said supply lead and a first terminal of a current limiting resistor whose second terminal is connected to the first plate of a storage capacitor having the second plate connected to said common lead, interconnection of said current limiting resistor and said storage capacitor is connected to the anode electrode of a Programmable Unijunction Transistor (PUT) whose cathode electrode is connected through a pulse forming resistor to said common lead, gate electrode of said PUT is connected through a biasing resistor to said common lead, said interconnection of gate electrode and biasing resistor is connected also to the cathode electrode of a compensating diode having anode electrode connected to interconnection of two PUT reference voltage resistors connected between said common and said supply lead, said PUT cathode electrode is connected to a pulse stretching circuit which includes anode electrode of a blocking diode whose cathode electrode is connected to the first plate of a capacitor, having the second plate connected to said common lead, a base resistor connected between the said diode-capacitor interconnection and a base electrode of an n-p-n transistor having emitter electrode connected to said common lead and the collector electrode connected through a relay coil to said supply lead, a transient protection diode is connected across said relay coil having cathode electrode connected to the positive end of said coil, said relay coil operating multiple sets of mutually isolated contacts, each set of contacts is utilized to pulse at least one sequencing circuit, the first set of contacts is utilized to pulse the first sequencing circuit which includes a normally open contact connected through a timing resistor to said supply lead, a common contact being connected through a current limiting resistor to the interconnection of the first plate of a storage capacitor, having second plate connected to said common lead, and an anode electrode of a PUT, whose cathode electrode is connected to an output terminal and to the first terminal of a cathode resistor, having second terminal connected to said common lead, the gate electrode of said PUT is connected through a biasing resistor to said common lead and to the cathode electrode of a biasing diode, whose anode electrode is connected to the interconnection of the two PUT reference voltage resistors connected between said common and said supply lead, the first sequence output terminal is also connected to the gate electrode of the first Silicon Controlled Rectifier (SCR) having the cathode electrode connected to said common lead and anode electrode connected through a first anode resistor to said supply lead, said anode electrode is also connected through a first base resistor to the base electrode of a first p-n-p transistor whose emitter electrode is connected to said supply lead and, collector electrode connected to the next sequencing circuit thus acts as the first supply lead, a second set of contacts which consists of a normally open contact and a common contact, these contacts being used to pulse a second sequencing circuit, which is of identical configuration as described first sequencing circuit, said second set of contacts operates associated circuit after the first sequencing time interval is over, said second sequence circuit being able to deliver a pulse at the end of said second sequence interval, and supply the power to the third sequencing circuit, an nth set of contacts which consists of a normally open contact and a common contact, these contacts are used to pulse the nth sequencing circuit, n being an integer larger than two, normally open contact is connEcted to the first terminal of the nth timing resistor whose second terminal is connected to the collector electrode of n - 1st sequencing circuit, said collector electrode acting as the n-1st supply lead, the common contact is connected through the nth limiting resistor to the first plate of an nth storage capacitor which has the second plate connected to said common lead, said first plate is also connected to the anode electrode of the nth PUT having cathode electrode connected through the nth cathode resistor to said common lead, said cathode is also connected to an nth output terminal, gate electrode of said nth PUT is connected through an nth biasing resistor to said common lead, said interconnection of biasing resistor and gate electrode is connected also to the cathode electrode of an nth compensating diode whose anode electrode is connected to the interconnection of the two nth PUT reference voltage resistors connected between said common and said n - 1st supply lead, said nth sequence circuit being able to produce a pulse at the end of the nth sequence interval.

Claim 8

The circuit of claim 5 and having said timing resistor adjustable to provide adjustable clock frequency which causes the change in duration of all sequences.

Claim 9

The circuit of claim 5 and having said first timing resistor adjustable, and said nth timing resistor adjustable to provide independently adjustable interval in each and every sequence.

Claim 10

The circuit of claim 5 having one single sequence by provision of a single set of contacts and a single sequencing circuit.