US3858207A — Range sensing target detecting device

Claim 1

Independent Claim 233 words

In a guided missile range sensing target detecting device, the combination comprising: a. a plurlity of target gate circuits for receiving video signals reflected from a target, b. target gate control means coupled to said plurality of target gate circuits for controlling the time interval each gate is open, c. peak detector circuit means having an input for receiving and producing an output proportional to the amplitude of the reflected video signals, d. delay filter circuit means coupled to each of said target gate circuits for attenuating signals which have a pulse width less than a predetermined value, e. variable threshold circuit means coupled to each of said delay filter circuit means for passing only the video signals received from said delay filter circuit means when they exceed the output signal from said peak detector circuit, f. target count circuit means coupled to each of said variable threshold circuit means for producing an output pulse in response to a predetermined number of video pulses received from said variable threshold circuit means within a predetermined time interval, g. a plurality of computer circuit means each having a first input coupled to the output of a target count circuit means and having a second input for receiving a voltge proportional to missile to target closing velocity for producing an output firing pulse in response to the presence of a pulse from said target count circuit.

Claim 2

Dependent Claim 233 words

In a guided missile range sensing target detecting device, the combination comprising: a. a plurlity of target gate circuits for receiving video signals reflected from a target, b. target gate control means coupled to said plurality of target gate circuits for controlling the time interval each gate is open, c. peak detector circuit means having an input for receiving and producing an output proportional to the amplitude of the reflected video signals, d. delay filter circuit means coupled to each of said target gate circuits for attenuating signals which have a pulse width less than a predetermined value, e. variable threshold circuit means coupled to each of said delay filter circuit means for passing only the video signals received from said delay filter circuit means when they exceed the output signal from said peak detector circuit, f. target count circuit means coupled to each of said variable threshold circuit means for producing an output pulse in response to a predetermined number of video pulses received from said variable threshold circuit means within a predetermined time interval, g. a plurality of computer circuit means each having a first input coupled to the output of a target count circuit means and having a second input for receiving a voltge proportional to missile to target closing velocity for producing an output firing pulse in response to the presence of a pulse from said target count circuit.

Claim 3

Dependent Claim 102 words

In the detecting device of claim 1 wherein each of said target gate circuits comprises: a. first and second transistors each having a base, emitter and a collector, b. the base of said first transistor being coupled to an input terminal for receiving said video signals, c. the base of said second transistor being coupled to said target gate control means, d. the collector of said second transistor being connected to the base of said first transistor, e. the emitter of said first transistor being connected to an output terminal and through a load resistor to the emitter of said second transistor.

Claim 4

Dependent Claim 44 words

The detecting device of claim 1 wherein said delay filter circuit means provides a sufficient delay of the video signal passed to permit the output voltage of said peak detector resulting from the same video signal to reach said variable threshold circuit means first.

Claim 5

Dependent Claim 199 words

The detecting device of claim 1 wherein said target gate control means comprises: a. an input terminal coupled to receive input pulses from a periodic pulse generating means, b. a variable width blocking oscillator having an input coupled to said input terminal for producing a series of output pulses in response to the periodic pulses at said input terminal, c. a first fixed width blocking oscillator coupled directly to said variable width blocking oscillator for producing a first series of gating pulses, d. a first delay circuit having a first predetermined delay coupled to the output of said variable width blocking oscillator, e. a second fixed width blocking oscillator coupled to said delay circuit for producing a second series of gating pulses delayed with respect to said first series of timing pulses by the amount of said first predetermined delay, f. a second delay circuit having a delay equal to that of said first delay circuit, g. a third fixed width blocking oscillator coupled to said second delay circuit for producing a series of gating pulses delayed with respect to said first series of gating pulses by the amount of delay of said first and second delay circuits combined.

Claim 6

Dependent Claim 45 words

The detecting device of claim 1 wherein said computer circuit comprises a monostable multivibrator triggered by the output of said target count circUit and biased by a voltage proportional to the missile to target closing velocity as modified to represent slant range to the target.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1977-12-30	1978-07-01	1978-12-31	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1981-12-30	1982-07-01	1982-12-31	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1985-12-30	1986-07-01	1986-12-31	$7700.00	Window Closed / Lapsed

Range sensing target detecting device

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