D.c. motor speed control system through phase control and phase locking circuit

Claim 1

A system for controlling the speed of a d.c. motor through a phase control and phase locking circuit comprising: timing means to supply a sequence of timing pulses with a frequency representing the desired speed of the motor; means responsive to the motor speed for supplying a sequence of tachometric pulses, with a frequency representing the real speed of the motor; a binary unidirectional shift register with at least four storage cells to receive and store said timing pulses and said tachometric pulses in the order in which they are received; said timing pulses being stored as binary information of a first logic value; said tachometric pulses being stored as binary information of a second logic value; decoding means to decode the content of said shift register means and to supply a binary signal whose logic value is dependent on the contents of said shift register means; and means to convert said binary signal to a control voltage and to supply said motor with said control voltage.

Claim 2

A system for controlling the speed of a d.c. motor through a phase control and phase locking circuit comprising: timing means to supply a sequence of timing pulses with a frequency representing the desired speed of the motor; means responsive to the motor speed for supplying a sequence of tachometric pulses, with a frequency representing the real speed of the motor; a binary unidirectional shift register with at least four storage cells to receive and store said timing pulses and said tachometric pulses in the order in which they are received; said timing pulses being stored as binary information of a first logic value; said tachometric pulses being stored as binary information of a second logic value; decoding means to decode the content of said shift register means and to supply a binary signal whose logic value is dependent on the contents of said shift register means; and means to convert said binary signal to a control voltage and to supply said motor with said control voltage.

Claim 5

A system for controlling the speed of a d.c. motor through a phase control and a phase locking circuit comprising: timing means to supply a sequence of timing pulses with a frequency representing the desired speed of the motor; means responsive to the motor speed for supplying a sequence of tachometric pulses, with a frequency representing the real speed of the motor; a binary unidirectional shift register having a timing input a serial input and at least four storage cells and one output for each storage cell, said timing pulses and said tachometric pulses being applied to said timing input, said timing pulses being further applied to said serial input, whereby said timing pulses are stored in said shift register as binary information of a first logic value and said tachometric pulses are stored in said shift register as binary information of a second logic value; decoding means to decode the content of said shift register and to supply a binary signal whose logic value is dependent on the contents of said shift register, and means to convert said binary signal to a control voltage and to supply said motor with said control voltage.

Claim 6

A system for controlling the speed of a d.c. motor through a phase control and a phase locking circuit comprising: timing means to supply a sequence of timing pulses with a frequency representing the desired speed of the motor; means responsive to the motor speed for supplying a sequence of tachometric pulses, with a frequency representing the real speed of the motor; a binary unidirectional shift register having a timing input a serial input and at least four storage cells and one output for each storage cell, said timing pulses and said tachometric pulses being applied to said timing input, said timing pulses being further applied to said serial input, whereby said timing pulses are stored in said shift register as binary information of a first logic value and said tachometric pulses are stored in said shift register as binary information of a second logic value; decoding means to decode the content of said shift register and to supply a binary signal whose logic value is dependent on the contents of said shift register, and means to convert said binary signal to a control voltage and to supply said motor with said control voltage.

Claim 7

A system for controlling the speed of a d.c. motor through a phase control and a phase locking circuit comprising: timing means to supply a sequence of timing pulses with a frequency representing the desired speed of the motor; means responsive to the motor speed for supplying a sequence of tachometric pulses with a frequency representing the real speed of the motor, a binary unidirectional shift register having a timing input a serial input and at least four storage cells and one output for each storage cell, said timing pulses and said tachometric pulses being applied to said timing iNput, said timing pulses being further applied to said serial input, whereby said timing pulses are stored in said shift register as binary information of a first logic value and said tachometric pulses are stored in said shift register as binary information of a second logic value, decoding means to decode the content of said shift register and to supply a binary signal whose logic value is dependent on the contents of said shift register and means to convert said binary signal to a control voltage and to supply said motor with said control voltage.

Claim 8

A system for controlling the speed of a d.c. motor through a phase control and a phase locking circuit comprising: timing means to supply a sequence of timing pulses with a frequency representing the desired speed of the motor; means responsive to the motor speed for supplying a sequence of tachometric pulses with a frequency representing the real speed of the motor, a binary unidirectional shift register having a timing input a serial input and at least four storage cells and one output for each storage cell, said timing pulses and said tachometric pulses being applied to said timing iNput, said timing pulses being further applied to said serial input, whereby said timing pulses are stored in said shift register as binary information of a first logic value and said tachometric pulses are stored in said shift register as binary information of a second logic value, decoding means to decode the content of said shift register and to supply a binary signal whose logic value is dependent on the contents of said shift register and means to convert said binary signal to a control voltage and to supply said motor with said control voltage.

Claim 9

A system for controlling the speed of a d.c. motor, comprising in combination: reference means for producing periodic reference pulses of selected frequency; tachometric means for producing periodic tachometric pulses of a frequency related to the speed of an associated d.c. motor; serial shift register means having a data input, a clock input and a plurality of parallel outputs; said reference pulses and said tachometric pulses being connected to said clock input of said shift register means for causing data shift in said register means in response to either one of said pulses, and said reference pulses being connected to said data input of the shift register means whereby data input of one logic level periodically is present at said data input at said selected frequency of the reference pulses whereas data input of the opposite logic level is present at said data input during reference interpulse periods so that data shifted into said shift registering means and the corresponding logic levels at said parallel outputs thereof depend upon the relative frequencies of said reference pulses and said tachometric pulses, and the frequency of said tachometric pulses when the d.c. motor is near a desired speed being related to said selected frequency such that a unique combination of said logic levels periodically is present at said parallel outputs; and decoding means connected to said parallel outputs of the shift register means and responsive to said periodic unique combination of logic levels for producing an output signal to control the associated d.c. motor to said desired speed.

Claim 10

A system for controlling the speed of a d.c. motor, comprising in combination: reference means for producing periodic reference pulses of selected frequency; tachometric means for producing periodic tachometric pulses of a frequency related to the speed of an associated d.c. motor; serial shift register means having a data input, a clock input and a plurality of parallel outputs; said reference pulses and said tachometric pulses being connected to said clock input of said shift register means for causing data shift in said register means in response to either one of said pulses, and said reference pulses being connected to said data input of the shift register means whereby data input of one logic level periodically is present at said data input at said selected frequency of the reference pulses whereas data input of the opposite logic level is present at said data input during reference interpulse periods so that data shifted into said shift registering means and the corresponding logic levels at said parallel outputs thereof depend upon the relative frequencies of said reference pulses and said tachometric pulses, and the frequency of said tachometric pulses when the d.c. motor is near a desired speed being related to said selected frequency such that a unique combination of said logic levels periodically is present at said parallel outputs; and decoding means connected to said parallel outputs of the shift register means and responsive to said periodic unique combination of logic levels for producing an output signal to control the associated d.c. motor to said desired speed.