US3858085A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital raster generator
Assignee: United States Department of the Navy
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Filing: 1973-07-09
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Granted: 1974-12-31
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Expires: 1993-07-09
Abstract
Abstract A digital raster signal generator is disclosed in combination with a sonar or radar and a cathode ray tube for producing a sector scan display of acquired targets. Included therein is a digital channel counter, a digital range counter, a reference digital-to-analog converter, a bipolar digital sine read only memory, a bipolar digital cosine read only memory, and a pair of multiplying digital-to-analog converters interconnected in such manner as to effect such horizontal and vertical sweep voltages as will produce the aforesaid sector scan display of acquired targets on the face of said cathode ray tube.
Inventors
- 👤 C Dildy
- 👤 A Dettbarn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 11:24
CPC Classifications
H; H03; H03K; H03K4/00; H03K4/02; H03K4/026; G; G01; G01S; G01S7/00; G01S7/02; G01S7/04; G01S7/06; G01S7/10; G01S7/12; G01S7/14
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
292 words
An apparatus of the character described, comprising in combination: means for producing a basic timing signal having a predetermined frequency; a programmable first digital counter, having a predetermined number of stages, a clock input, a trigger output, and an address output, with the clock input thereof connected to the output of said basic timing signal producing means and with the address output thereof adapted for being connected to a predetermined multi-channel utilization apparatus; a second digital counter, having a predetermined number of stages, a data signal input, a data signal output, and an actuation trigger output for being connected to an actuation input of the aforesaid predetermined multi-channel utilization apparatus, with the data signal input thereof connected to the trigger output of said programmable first digital counter; a reference digital-to-analog converter, having a predetermined bit capacity, connected to the data signal output of said second digital counter; a first programmable read only memory, having a predetermined bit capacity, connected to the address output of the aforesaid first digital counter; a first multiplying digital-to-analog converter, having a predetermined bit capacity, a pair of inputs, and an output, with one of the inputs thereof connected to the output of the aforesaid reference digital-to-analog converter, and with the other input thereof connected to the output of said first programmable read only memory; a second programmable read only memory, having a predetermined bit capacity, connected to the address output of the aforesaid first digital counter; and a second multiplying digital-to-analog converter, having a predetermined bit capacity, a pair of inputs, and an output, with one of the inputs thereof connected to the output of the aforesaid reference digital-to-analog converter, and with the other input thereof connected to the output of said second pRogrammable read only memory.
Claim 2
Independent Claim
292 words
An apparatus of the character described, comprising in combination: means for producing a basic timing signal having a predetermined frequency; a programmable first digital counter, having a predetermined number of stages, a clock input, a trigger output, and an address output, with the clock input thereof connected to the output of said basic timing signal producing means and with the address output thereof adapted for being connected to a predetermined multi-channel utilization apparatus; a second digital counter, having a predetermined number of stages, a data signal input, a data signal output, and an actuation trigger output for being connected to an actuation input of the aforesaid predetermined multi-channel utilization apparatus, with the data signal input thereof connected to the trigger output of said programmable first digital counter; a reference digital-to-analog converter, having a predetermined bit capacity, connected to the data signal output of said second digital counter; a first programmable read only memory, having a predetermined bit capacity, connected to the address output of the aforesaid first digital counter; a first multiplying digital-to-analog converter, having a predetermined bit capacity, a pair of inputs, and an output, with one of the inputs thereof connected to the output of the aforesaid reference digital-to-analog converter, and with the other input thereof connected to the output of said first programmable read only memory; a second programmable read only memory, having a predetermined bit capacity, connected to the address output of the aforesaid first digital counter; and a second multiplying digital-to-analog converter, having a predetermined bit capacity, a pair of inputs, and an output, with one of the inputs thereof connected to the output of the aforesaid reference digital-to-analog converter, and with the other input thereof connected to the output of said second pRogrammable read only memory.
Claim 3
Dependent Claim
23 words
The device of claim 1, wherein said means for producing a basic timing signal having a predetermined frequency comprises an adjustable frequency oscillator.
Claim 4
Dependent Claim
32 words
The device of claim 1, wherein said means for producing a basic timing signal having a predetermined frequency comprises an oscillator for producing an output signal having a frequency of 798 KHz.
Claim 5
Dependent Claim
51 words
The device of claim 1 wherein said programmable first digital counter, having a predetermined number of stages, a clock input, a trigger output, and an address output, with the clock input thereof connected to the output of said basic timing signal producing means comprises a programmable six stage digital channel counter.
Claim 6
Dependent Claim
68 words
The device of claim 1, wherein said second digital counter, having a predetermined number of stages, a data signal input, a data signal output, and an actuation trigger output adapted for being connected to an actuation input of the aforesaid predetermined multichannel utilization apparatus, with the data signal input thereof connected to the trigger output of said programmable first digital counter comprises a nine stage digital range counter.
Claim 7
Dependent Claim
32 words
The device of claim 1, wherein said reference digital-to-analog converter, having a predetermined bit capacity, connected to the data signal output of said second digital counter comprises a nine bit digital-to-analog converter.
Claim 8
Dependent Claim
57 words
The device of claim 1, wherein said first programmable read only memory, having a predetermined bit capacity, connected to the address signal output of said first digital counter comprises a 512 bit digital read only memory that is programmed for converting the address signal supplied thereto into an output signal that is proportional to the sine thereof.
Claim 9
Dependent Claim
63 words
The device of claim 1, wherein said first multiplying digital-to-analog converter, having a predetermined bit capacity, a pair of inputs, and an output, with one of the inputs thereof connected to the output of the aforesaid reference digital-to-analog converter, and with the other input thereof connected to the output of said first programmable read only memory comprises an 8 bit multiplying digital-to-analog converter.
Claim 10
Dependent Claim
56 words
The device of claim 1, wherein said second programmable read only memory, having a predetermined bit capacity, connected to the address output of said first digital counter comprises a 512 bit digital read only memory that is programmed for converting the address signal supplied thereto into an output signal that is proportional to the cosine thereof.
Claim 11
Dependent Claim
63 words
The device of claim 1, wherein said second multiplying digital-to-analog converter, having a predetermined bit capacity, a pair of inputs, and an output, with one of the inputs thereof connected to the output of the aforesaid reference digital-to-analog converter, and with the other input thereof connected to the output of said second programmable read only memory comprises an eight bit multiplying digital-to-analog converter.
Claim 12
Dependent Claim
65 words
The invention of claim 1, further characterized by another utilization apparatus having a plurality of inputs, with one of the inputs thereof connected to the output of said first multiplying digital-to-analog converter, with another of the inputs thereof connected to the output of said second multiplying digital-to-analog converter, and with the remaining inputs thereof adapted for being connected for response to predetermined signals supplied thereto.
Claim 13
Dependent Claim
83 words
The invention of claim 1, further characterized by a readout having a horizontal coordinant sweep input, a vertical coordinant sweep input, and a data signal input, with the horizontal coordinant sweep input thereof connected to the output of said first multiplying digital-to-analog converter, and with the vertical coordinant sweep input thereof connected to the output of the aforesaid second multiplying digital-to-analog converter, and with the data signal input thereof adapted for being connected to the data signal outpUt of said predetermined utilization apparatus.
Claim 14
Dependent Claim
79 words
The invention of claim 12, wherein said predetermined utilization apparatus comprises a multi-channel sonar having a channel scanner signal input, an actuation signal input, and a data signal output, with the channel scanner input thereof connected to the address output of the aforesaid first digital counter, with the actuation trigger input thereof connected to the actuation trigger output of said second digital counter, and with the data signal output thereof connected to the data signal input of said readout.
Claim 15
Dependent Claim
79 words
The invention of claim 12, wherein said predetermined utilization apparatus comprises a multi-channel radar having a channel scanner signal input, an actuation input, and a data signal output, with the channel scanner input thereof connected to the address output of the aforesaid first digital counter, with the actuation trigger input thereof connected to the actuation trigger output of said second digital counter, and with the data signal output thereof connected to the data signal input of the aforesaid readout.
Claim 16
Dependent Claim
87 words
The invention of claim 1, further characterized by a cathode ray tube having a horizontal coordinant sweep input, a vertical coordinant sweep input, and a data signal input, with the horizontal coordinant sweep input thereof connected to the output of the aforesaid first multiplying digital-to-analog converter, with the vertical coordinant sweep input thereof connected to the output of the aforesaid second multiplying digital-to-analog converter, and with the data signal input thereof adapted for being connected for response to the video output signal of said predetermined utilization apparatus.
Claim 17
Dependent Claim
80 words
The invention of claim 15, wherein said predetermined utilization apparatus comprises a multi-channel sonar having a channel scanner input, an actuation input, and a video signal output, with the channel scanner input thereof connected to the address output of the aforesaid first digital counter, with the actuator trigger input thereof connected to the actuator trigger output of said second digital counter, and with the video signal output thereof connected to the video signal input of the aforesaid cathode ray tube.
Claim 18
Dependent Claim
80 words
The invention of claim 15, wherein said predetermined utilization apparatus comprises a multi-channel radar having a channel scanner input, an actuation input, and a video signal output, with the channel scanner input thereof connected to the address output of the aforesaid first digital counter, with the actuation trigger input thereof connected to the actuator trigger output of said second digital counter, and with the video signal output thereof connected to the video signal input of the aforesaid cathode ray tube.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-30 | 1978-07-01 | 1978-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-30 | 1982-07-01 | 1982-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-30 | 1986-07-01 | 1986-12-31 | $7700.00 | Window Closed / Lapsed |