US3855541A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current proportioning circuit
Assignee: Individual
•
Filing: 1973-10-05
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Granted: 1974-12-17
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Expires: 1993-10-05
Abstract
Abstract A terminal to which an input current is applied is connected to the base and the collector electrodes of a first transistor by a first and a second direct current conductive path, respectively. Each of these paths contains the same number of semiconductor junctions, poled to be forward biased by a fraction of the input current. The emitter-to-collector potential of the first transistor is applied to the base-emitter junction of a second transistor. The second transistor responds with a collector current which is proportional to the input current divided by substantially the following quantity: the common-emitter forward current gain (hfe) of the first transistor raised to an integral power.
Inventors
- 👤 A Leidich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:25
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/265; H; H03; H03F; H03F3/00; H03F3/34; H03F3/343; H03F3/347
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
224 words
A circuit for conditioning a first transistor to have an output current flow in its emitter-to-collector path which is a fraction of the current flowing in the emitter-to-collector path of a second transistor, each of said first and second transistors also having a base-to-emitter path and a base electrode, said conditioning circuit comprising, in combination: an input terminal for an input current; an output terminal for said output current to which said first transistor collector electrode is connected; a common terminal to which the emitter electrodes of said first and said second transistors are connected; two non-linear circuit means having substantially the same current versus voltage characteristics each of said non-linear circuits maintaining an offset potential thereacross logarithmically related to the current flow therethrough, one said non-linear circuit means connected between said input terminal and said collector electrode of said second transistor for conducting a first portion of said input current flowing as the collector current of said second transistor and the other such non-linear circuit means connected between said input terminal and the base electrode of said second transistor for conducting a second portion of said input current flowing as the base current of said second transistor; and means for maintaining the potential across the base-to-emitter path of said first transistor at the potential appearing across the collector-to-emitter path of said second transistor.
Claim 2
Dependent Claim
224 words
A circuit for conditioning a first transistor to have an output current flow in its emitter-to-collector path which is a fraction of the current flowing in the emitter-to-collector path of a second transistor, each of said first and second transistors also having a base-to-emitter path and a base electrode, said conditioning circuit comprising, in combination: an input terminal for an input current; an output terminal for said output current to which said first transistor collector electrode is connected; a common terminal to which the emitter electrodes of said first and said second transistors are connected; two non-linear circuit means having substantially the same current versus voltage characteristics each of said non-linear circuits maintaining an offset potential thereacross logarithmically related to the current flow therethrough, one said non-linear circuit means connected between said input terminal and said collector electrode of said second transistor for conducting a first portion of said input current flowing as the collector current of said second transistor and the other such non-linear circuit means connected between said input terminal and the base electrode of said second transistor for conducting a second portion of said input current flowing as the base current of said second transistor; and means for maintaining the potential across the base-to-emitter path of said first transistor at the potential appearing across the collector-to-emitter path of said second transistor.
Claim 3
Dependent Claim
176 words
In combination: first and second transistors, each having a base electrode and an emitter electrode with a base-emitter junction therebetween and each having a collector electrode, said first transistor base electrode being connected to said second transistor collector electrode; a first terminal for connection to a reFerence potential to which the emitter electrodes of said first and said second transistors are connected; a second terminal connected to said first transistor collector electrode for connection to current utilization means; a third terminal for application of input current; a first and a second direct current conductive path connecting said third terminal to the base and the collector electrodes, respectively, of said second transistor, each of said first and said second conductive paths being serially connected in the forward direction, through an equal number n of semiconductor junction devices, where n is an integer equal to at least one, whereby said first transistor collector current will respond to said input current in substantially inverse proportion to the common-emitter forward current gain of said second transistor raised to a power.
Claim 4
Dependent Claim
176 words
In combination: first and second transistors, each having a base electrode and an emitter electrode with a base-emitter junction therebetween and each having a collector electrode, said first transistor base electrode being connected to said second transistor collector electrode; a first terminal for connection to a reFerence potential to which the emitter electrodes of said first and said second transistors are connected; a second terminal connected to said first transistor collector electrode for connection to current utilization means; a third terminal for application of input current; a first and a second direct current conductive path connecting said third terminal to the base and the collector electrodes, respectively, of said second transistor, each of said first and said second conductive paths being serially connected in the forward direction, through an equal number n of semiconductor junction devices, where n is an integer equal to at least one, whereby said first transistor collector current will respond to said input current in substantially inverse proportion to the common-emitter forward current gain of said second transistor raised to a power.
Claim 5
Dependent Claim
43 words
The combination set forth in claim 2, wherein each of said semiconductor junction devices comprises a transistor having a base electrode and an emitter electrode with a base-emitter junction therebetween and having a collector electrode to which its said base electrode is connected.
Claim 6
Dependent Claim
75 words
The combination set forth in claim 2 wherein said first path includes the base-emitter junction of a third transistor, said third transistor also having a collector electrode, said third transistor base electrode being connected to said third terminal, said third transistor base-emitter junction providing a said semiconductor junction device in said first direct current conductive path, and means for applying an operating potential for said third transistor between its collector electrode and said first terminal.
Claim 7
Dependent Claim
54 words
The combination set forth in claim 4 wherein each of the 2n-1 rest of the semiconductor junction devices in said first and said second paths comprises a transistor having a base electrode and an emitter electrode with a base-emitter junction therebetween, each having a collector electrode to which its said base electrode is connected.
Claim 8
Dependent Claim
44 words
The combination set forth in claim 2 further including: a fourth terminal for connection to a point of operating potential relative to said reference potential; and a resistive element included in a direct current conductive coupling of said third terminal to said fourth terminal.
Claim 9
Dependent Claim
89 words
The combination set forth in claim 2 further including: a current mirror amplifier having an input circuit connected to said second terminal and having an output circuit; a third transistor having a base electrode direct coupled to said current mirror amplifier output circuit, having an emitter electrode connected to said first terminal and having a collector electrode; a fourth terminal for connection to a supply of operating potential referred to said reference potential; and load means connected between said fourth terminal and the collector electrode of said third transistor.
Claim 10
Dependent Claim
95 words
The combination set forth in claim 2 further including: first and second current mirror amplifiers, each having an input circuit and an output circuit, said first current mirror amplifier input circuit being connected to said second terminal; a supply of input current coupled to said third terminal by means of said second current mirror amplifier input circuit; a third transistor having a base electrode connected to said first current mirror output circuit, having an emitter electrode direct coupled to said first terminal and having a collector electrode connected to said second current mirror output circuit.
Claim 11
Dependent Claim
141 words
The combination set forth in claim 2 further including: first and second current mirror amplifiers, each having an input circuit and an output circuit, said first current mirror amplifier input circuit being connected to said second terminal; a supply of input current coupled to said third terminal by means of said second current mirror amplifier input circuit; n further transistors, each having a base eleCtrode and an emitter electrode with a base-emitter junction therebetween and a collector electrode, said n further transistors being connected in cascade combination with their base-emitter junctions being serially connected, the base electrode of the first of said n further transistors in said cascade combination being connected to said first current mirror amplifier output circuit, and the collector electrode of the last of said n further transistors being connected to said second current mirror amplifier output circuit.
References Cited (Backward Citations)
US3717821A
Cited
US3721893A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-16 | 1978-06-17 | 1978-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-16 | 1982-06-17 | 1982-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-16 | 1986-06-17 | 1986-12-17 | $7700.00 | Window Closed / Lapsed |