Multiple frequency band frequency synthesizer

Claim 2

A frequency synthesizer to generate one at a time a plurality of first signals each having a different selected frequency in each of a plurality of different frequency bands comprising: a voltage controlled oscillator capable of generating one at a time a plurality of second signals each having a different frequency in a given frequency band common to and predeterminedly related to said plurality of different frequency bands, the frequencies of said second signals being predeterminedly related to the frequencies of said first signals in each of said plurality of different frequency bands; first means coupled to the output of said oscillator to frequency multiply the output signal of said oscillator by a plurality of different multiplication factors to provide one at a time said plurality of first signals in each of said plurality of different frequency bands; and a single phase locked loop coupled between the input and output of said voltage controlled oscillator to control the generation of said plurality of second signals; said phase locked loop including second means coupled between the input and the output of said oscillator to divide the output signal of said oscillator by a plurality of different division factors to select the frequency of each of said first signals at the output of said first means, the frequencies of said first signals having a different constant incremental frequency step in each of said plurality of frequency bands; said first means including a plurality of series circuits each having a frequency multiplier and a band pass filter coupled in series with each other and to the output of said voltage controlled oscillator, said series circuits being equal in number to said plurality of different frequency bands, each of said frequency multipliers having a different multiplication factor, and each of said series circuits defining a different one of said plurality of different frequency bands; and said second means further selecting a desired one of said plurality of different frequency bands as defined by an appropriate one of said series circuits.

Claim 3

A frequency synthesizer according to claim 1, further including an automatic level control circuit having a level controlled amplifier coupled between the output of said voltage controlled oscillator and each of said frequency multipliers, a plurality of level detectors each coupled to the output of a different one of said band pass filters, each of said level detectors producing a control signal proportional to the amplitude of the output signal of an associated one of said band pass fIlters, a control signal amplifier having its output coupled to a control input of said level controlled amplifier for amplitude control in accordance with a selected one of said control signals, and a switch controlled by said second means coupled between the input of said control signal amplifier and the output of said level detectors.

Claim 4

A frequency synthesizer according to claim 2, wherein said phase locked loop includes a reference signal oscillator generating a signal having a predetermined frequency, a first frequency divider coupled to the output of said reference oscillator to divide said predetermined frequency by a first given division factor, a phase detector having a first input and a second input, said first input being coupled to the output of said first frequency divider, a reference signal frequency multiplier coupled to the output of said reference oscillator to multiply said predetermined frequency by a given multiplication factor, a mixer coupled to the output of said level controlled amplifier and the output of said reference signal frequency multiplier, a second frequency divider coupled to the output of said mixer to divide the frequency of the output signal of said mixer by a second given division factor different than said first given division factor, said second means coupled between the output of said second frequency divider and said second input of said phase detector, and a low pass loop filter coupled between the output of said phase detector and a control input of said voltage controlled oscillator.

Claim 5

A frequency synthesizer according to claim 3, wherein said second means includes a programmable frequency divider having a programmed division factor equal to N, where N is a programmed integer.

Claim 6

A frequency synthesizer according to claim 4, wherein N has a different range of values for each of said plurality of different frequency bands.

Claim 7

A frequency synthesizer according to claim 5, wherein said second means further includes a third frequency divider coupled between the output of said programmable frequency divider and said second input of said phase detector, said third frequency divider having a selected one of a plurality of division factors, said selected one of said plurality of division factors being determined by said desired one of said plurality of different frequency bands.

Claim 8

A frequency synthesizer according to claim 6, wherein said first, second, third and programmable frequency dividers are binary frequency dividers.

Claim 9

A frequency synthesizer according to claim 7, wherein said second means further includes third means to program said programmable frequency divider to achieve a desired value of N, to select a desired division factor for said third frequency divider and to select said desired one of said plurality of different frequency bands.

Claim 10

A frequency synthesizer according to claim 8, wherein said third means includes a plurality of frequency selecting switches, each of said switches generating a 9''s complemented binary coded decimal signal representing the decimal value to which each of said switches are set, said coded signal from the least significant of said switches being coupled directly to said programmable frequency divider to program a first portion of said programmable frequency divider; a frequency band detector coupled to a predetermined number of the most significant of said switches to produce a band selection signal indicating which one of said plurality of different frequency bands said switches have selected; a selection circuit coupled to the output of said programmable frequency divider and the output of said third frequency divider to divide the output signal from said programmable frequency divider by a division factor of said third frequency divider as selected by said band selection signal; binary adder means coupled to each of said switches between said lEast significant and said most significant switch to add a different constant value in digital form for each of said plurality of different frequency bands under control of said band selection signal to said 9''s complemented binary coded decimal signal coupled to said binary adder means, the resultant digital output from said binary adder means being coupled to said programmable frequency divider to program a second portion of said programmable frequency divider; and a detector coupled to said most significant one of said switches; at least one output of said binary adder means and said programmable frequency divider to produce a signal to program a third portion of said programmable frequency divider; the programming of said first, second and third portions of said programmable frequency divider determining the value of said division factor N.

Claim 11

A frequency synthesizer according to claim 9, wherein said 9''s complemented binary coded decimal signal from each of said switches includes four binary bits; said plurality of different frequency bands include a first frequency band, and a second frequency band; said plurality of frequency selecting switches include a first frequency selecting switch which is the most significant switch, a second frequency selecting switch which is the next most significant switch, a third frequency selecting switch which is the next most significant switch, a fourth frequency selecting switch which is the next most significant switch, and a fifth frequency selecting switch which is the least significant switch; and said plurality of division factors of said third frequency divider equals one for said first frequency band and an integral M greater than one for said second frequency band.

Claim 12

A frequency synthesizer according to claim 10, wherein said frequency band detector includes a first logic gate circuit coupled to said first and second switches responding to the binary condition of the penultimate significant weight bit of said coded decimal signal from said first switch and to the binary condition of the most significant and penultimate significant weight bits of said coded decimal signal from said second switch to produce a first binary signal representing said first frequency band and a second binary signal representing said second frequency band.

Claim 13

A frequency synthesizer according to claim 11, wherein said binary adder means includes a first binary adder coupled to said fourth switch and said first logic gate circuit to add a first digital signal representing the least significant decimal of a first constant value to said coded decimal signal from said fourth switch when said second binary signal is a binary ''''1'''' and said first binary signal is a binary ''''0'''' and to add a second digital signal representing the least significant decimal of a second constant value different than said first constant value to said coded decimal signal from said fourth switch when said first binary signal is a binary ''''1'''' and said second binary signal is a binary ''''0''''; a second logic gate circuit coupled to a carry output and each of the three most significant sum bits of said first binary adder to provide a binary ''''1'''' output when a coded output of said first binary adder is greater than nine; a second binary adder coupled to said second logic gate circuit and said first binary adder responding to the three most significant sum bits of said first binary adder and the binary condition of the output signal of said second logic gate circuit to produce the three most significant weight bits of a first program word, the least significant weight bit of said first program word being provided directly from said first binary adder; a third binary adder coupled to said third switch, said first logic gate circuit and said second logic gate circuit to add a third digital signal representing the penultimate most significanT decimal of said first constant value to said coded decimal signal from said third switch when said second binary signal is a binary ''''1'''' and said first binary signal is a binary ''''0'''' and to add a fourth digital signal representing the penultimate most significant decimal of said second constant value to said coded decimal signal from said third switch when said first binary signal is a binary ''''1'''' and said second binary signal is a binary ''''0''''; a third logic gate coupled to a carry output and each of the three most significant sum bits of said third binary adder to provide a binary ''''1'''' output when a coded output of said third binary adder is greater than nine; a fourth binary adder coupled to said third logic gate circuit and said third binary adder responding to the three most significant sum bits of said third binary adder and the binary condition of the output signal of said third logic gate circuit to produce the three most significant weight bits of a second program word, the least significant weight bit of said second program word being provided directly from said third binary adder; a fifth binary adder coupled to said second switch, said first logic gate circuit and said third logic gate circuit to add a fifth digital signal representing the most significant decimal of said first constant value to said coded decimal signal from said second switch when said second binary signal is a binary ''''1'''' and said first binary signal is a binary ''''0'''' and to add a sixth digital signal representing the most significant decimal of said second constant value to said coded decimal signal from said second switch when said first binary signal is a binary ''''1'''' and said second binary signal is a binary ''''0''''; a fourth logic gate circuit coupled to a carry output and each of the three most significant sum bits of said fifth binary adder to provide a binary ''''1'''' output when a coded output of said fifth binary adder is greater than nine; and a sixth binary adder coupled to said fourth logic gate circuit and said fifth binary adder responding to the three most significant sum bits of said fifth binary adder and the binary condition of the output signal of said fourth logic gate circuit to produce the three most significant weight bits of a third program word, the least significant weight bit of said third program word being provided directly from said fifth binary adder.

Claim 14

A frequency synthesizer according to claim 12, wherein said detector includes a fifth logic gate circuit coupled to said fourth logic gate circuit, said first switch and said first logic gate circuit to produce a fourth program word having only a least significant weight bit.

Claim 15

A frequency synthesizer according to claim 13, wherein said third frequency divider includes a modulo M counter coupled to said programmable frequency divider, wherein M is an integer; and said selection circuit includes a sixth logic gate circuit coupled to said programmable frequency divider, said modulo M counter and said first logic gate circuit responding to said second binary signal to couple the output of said programmable frequency divider directly to said phase detector when said second binary signal is a binary ''''0'''' and to couple the output of said programmable frequency divider to said modulo M counter prior to coupling to said phase detector when said second binary signal is a binary ''''1.''''

Claim 16

A frequency synthesizer according to claim 14, wherein said programmable frequency divider includes a units four stage decade presetable binary counter coupled directly to said fifth switch and preset by said coded decimal signal from said fifth switch; a tens four stage decade presetable binary counter coupled to said first and second binary adders and preset by said first program word; a hundreds four stage decade presetable binary counter coupled to said tens binary counter and said tHird and fourth binary adders and preset by said second program word; a thousands four stage decade presetable binary counter coupled to said hundreds binary counter and said fifth and sixth binary adders and preset by said third program word; a bistable device coupled to said thousands binary counter and said fifth logic gate circuit preset by said fourth program word; a prescaler binary counter coupled between said second frequency divider and said units and tens binary counter, said prescaler binary counter having one of two division factors; and a counter control circuit coupled to said units, tens, hundreds and thousands binary counters to control the counting thereof and coupled to said prescaler binary counter and said units binary counter to control the selection of the division factor of said prescaler binary counter.

Claim 17

A frequency synthesizer according to claim 15, wherein said modulo-M counter, said counter control circuit, said units, tens, hundreds and thousands binary counters and said bistabale devices include transistor transistor logic, and said prescaler binary counter includes emitter coupled logic; and further including an emitter coupled logic-to-transistor transistor logic converter coupled to the output of said prescaler binary counter, and a transistor transistor logic-to-emitter coupled logic converter coupled between a control input of said prescaler binary counter and said counter control circuit.

Claim 18

A frequency synthesizer according to claim 1, further including an automatic level control circuit having a level controlled amplifier coupled between the output of said voltage controlled oscillator and the input of said first means, a plurality of level detectors coupled to the output of said first means, each of said level detectors producing a control signal proportional to the amplitude of the output signal of an associated one of said plurality of different frequency bands, a control signal amplifier having its output coupled to a control input of said level controlled amplifier for amplitude control in accordance with a selected one of said control signals, and a switch controlled by said second means coupled between the input of said control signal amplifier and the output of said level detectors.

Claim 19

A frequency synthesizer according to claim 17, wherein said phase locked loop includes a reference signal oscillator generating a signal having a predetermined frequency, a first frequency divider coupled to the output of said reference oscillator to divide said predetermined frequency by a first given division factor, a phase detector having a first input and a second input, said first input being coupled to the output of said first frequency divider, a reference signal frequency multiplier coupled to the output of said reference oscillator to multiply said predetermined frequency by a given multiplication factor, a mixer coupled to the output of said level controlled amplifier and the output of said reference signal frequency multiplier, a second frequency divider coupled to the output of said mixer to divide the frequency of the output signal of said mixer by a second given division factor different than said first given division factor, said second means coupled between the output of said second frequency divider and said second input of said phase detector, and a low pass loop filter coupled between the output of said phase detector and a control input of said voltage controlled oscillator.

Claim 20

A frequency synthesizer according to claim 1, wherein said phase locked loop includes a reference signal oscillator generating a signal having a predetermined frequency, a first frequency divider coupled to the output of said reference oscillator to divide said predetermined frequency by a first given division factor, a phase detector having a first input and a second input, said first input being coupled to the output of said first frequency divider, a reference signal frequency multiplier coupled to the output of said reference oscillator to multiply said predetermined frequency by a given multiplication factor, a mixer coupled to the output of said voltage controlled oscillator and the output of said reference signal frequency multiplier, a second frequency divider coupled to the output of said mixer to divide the frequency of the output signal of said mixer by a second given division factor different than said first given division factor, said second means coupled between the output of said second frequency divider and said second input of said phase detector, and a low pass loop filter coupled between the output of said phase detector and a control input of said voltage controlled oscillator.

Claim 21

A frequency synthesizer according to claim 1, wherein said second means includes a programmable frequency divider having a programmed division factor equal to N, where N is a programmed integer.

Claim 22

A frequency synthesizer according to claim 20, wherein N has a different range of values for each of said plurality of different frequency bands.

Claim 23

A frequency synthesizer according to claim 21, wherein said second means further includes a frequency divider coupled to the output of said programmable frequency divider, said frequency divider having a selected one of a plurality of division factors, said selected one of said plurality of division factors being determined by said desired one of said plurality of different frequency bands.

Claim 24

A frequency synthesizer according to claim 22, wherein said frequency divider and said programmable frequency divider are binary frequency dividers.

Claim 25

A frequency synthesizer according to claim 23, wherein said second means further includes third means to program said programmable frequency divider to achieve a desired value of N, to select a desired division factor for said frequency divider and to select said desired one of said plurality of different frequency bands.

Claim 26

A frequency synthesizer according to claim 24, wherein said third means includes a plurality of frequency selecting switches, each of said switches generating a 9''s complemented binary coded decimal signal representing the decimal value to which each of said switches are set, said coded signal from the least significant of said switches being coupled directly to said programmable frequency divider to program a first portion of said programmable frequency divider; a frequency band detector coupled to a predetermined number of the most significant of said switches to produce a band selection signal indicating which one of said plurality of different frequency bands said switches have selected; a selection circuit coupled to the output of said programmable frequency divider and the output of said frequency divider to divide the output signal from said programmable frequency divider by a division factor of said frequency divider as selected by said band selection signal; binary adder means coupled to each of said switches between said least significant and said most significant switch to add a different constant value in digital form for each of said plurality of different frequency band under control of said band selection signal to said 9''s complemented binary coded decimal signal coupled to said binary adder means, the resultant digital output from said binary adder means being coupled to said programmable frequency divider to program a second portion of said programmable frequency divider; and a detector coupled to said most significant one of said switches, at least one output of said binary adder means and said programmable frequency divider to produce a signal to program a third portion of said programmable frequency divider; the programming of said first, second and third portions of said programmable frequency divider determining the value of said devIsion factor N.

Claim 27

A frequency synthesizer according to claim 25, wherein said 9''s complemented binary coded decimal signal from each of said switches includes four binary bits; said plurality of different frequency bands include a first frequency band, and a second frequency band; said plurality of frequency selecting switches includes a first frequency selecting switch which is the most significant switch, a second frequency selecting switch which is the next most significant switch, a third frequency selecting switch which is the next most significant switch, a fourth frequency selecting switch which is the next most significant switch, and a fifth frequency selecting switch which is the least significant switch; and said plurality of division factors of said frequency divider equals one for said first frequency band and an integral M greater than one for said second frequency band.

Claim 28

A frequency synthesizer according to claim 26, wherein said frequency band detector includes a first logic gate circuit coupled to said first and second switches responding to the binary condition of the penultimate significant weight bit of said coded decimal signal from said first switch and to the binary condition of the most significant and penultimate significant weight bits of said coded decimal signal from said second switch to produce a first binary signal representing said first frequency band and a second binary signal representing said second frequency band.

Claim 29

A frequency synthesizer according to claim 27, wherein said binary adder means includes a first binary adder coupled to said fourth switch and said first logic gate circuit to add a first digital signal representing the least significant decimal of a first constant value to said coded decimal signal from said fourth switch when said second binary signal is a binary ''''1'''' and said first binary signal is a binary ''''0'''' and to add a second digital signal representing the least significant decimal of a second constant value different than said first constant value to said coded decimal signal from said fourth switch when said first binary signal is a binary ''''1'''' and said second binary signal is a binary ''''0;'''' a second logic gate circuit coupled to a carry output and each of the three most significant sum bits of said first binary adder to provide a binary ''''1'''' output when a coded output of said first binary adder is greater than nine; a second binary adder coupled to said second logic gate circuit and said first binary adder responding to the three most significant sum bits of said first binary adder and the binary condition of the output signal of said second logic gate circuit to produce the three most significant weight bits of a first program word, the least significant weight bit of said first program word being provided from said first binary adder; a third binary adder coupled to said third switch, said first logic gate circuit and said second logic gate circuit to add a third digital signal representing the penultimate most significant decimal of said first contant value to said coded decimal signal from said third switch when said second binary signal is a binary ''''1'''' and said first binary signal is a binary ''''0'''' and to add a fourth digital signal representing the penultimate most significant decimal of said second constant value to said coded decimal signal from said third switch when said first binary signal is a binary ''''1'''' and said second binary signal is a binary ''''0''''; a third logic gate coupled to a carry output and each of the three most significant sum bits of said third binary adder to provide a binary ''''1'''' output when a coded output of said third binary adder is greater than nine; a fourth binary adder coupled to said third logic gate circuit and said third binary adder responding to the three most significant sum bits of said third binarY adder and the binary condition of the output signal of said third logic gate circuit to produce the three most significant weight bits of a second program word, the least significant weight bit of said second program word being provided directly from said third binary adder; a fifth binary adder coupled to said second switch, said first logic gate circuit and said third logic gate circuit to add a fifth digital signal representing the most significant decimal of said first constant value to said coded decimal signal from said second switch when said second binary signal is a binary ''''1'''' and said first binary signal is a binary ''''0'''' and to add a sixth digital signal representing the most significant decimal of said second constant value to said coded decimal signal from said second switch when said first binary signal is a binary ''''1'''' and said second binary signal is a binary ''''0''''; a fourth logic gate circuit coupled to a carry output and each of the three most significant sum bits of said fifth binary adder to provide a binary ''''1'''' output when a coded output of said fifth binary adder is greater than nine; and a sixth binary adder coupled to said fourth logic gate circuit and said fifth binary adder responding to the three most significant sum bits of said fifth binary adder and the binary condition of the output signal of said fourth logic gate circuit to produce the three most significant weight bits of a third program word, the least significant weight bit of said third program word being provided directly from said fifth binary adder.

Claim 30

A frequency synthesizer according to claim 28, wherein said detector includes a fifth logic gate circuit coupled to said fourth logic gate circuit, said first switch and said first logic gate circuit to produce a fourth program word having only a least significant weight bit.

Claim 31

A frequency synthesizer according to claim 29, wherein said frequency divider includes a modulo M counter coupled to said programmable frequency divider, wherein M is an integer; said selection circuit includes a sixth logic gate circuit coupled to said programmable frequency divider, said modulo M counter and said first logic gate circuit responding to said second binary signal to couple the output of said programmable frequency divider directly to the output of said second means when said second binary signal is a binary ''''0'''' and to couple the output of said programmable frequency divider to said modulo M counter prior to coupling to the output of said second means when said second binary signal is a binary ''''1''''.

Claim 32

A frequency synthesizer according to claim 30, wherein said programmable frequency divider includes a units four stage decade presetable binary counter coupled directly to said fifth switch and preset by said coded decimal signal from said fifth switch; a tens four stage decade presetable binary counter coupled to said first and second binary adders and preset by said first program word; a hundreds four stage decade presetable binary counter coupled to said tens binary counter and said third and fourth binary adders and preset by said second program word; a thousands four stage decade presetable binary counter coupled to said hundreds binary counter and said fifth and sixth binary adders and preset by said third program word; a bistable device coupled to said thousands binary counter and said fifth logic gate circuit preset by said fourth program word; a prescaler binary counter coupled between said second frequency divider and said units and tens binary counter, said prescaler binary counter having one of two division factors; and a counter control circuit coupled to said units, tens, hundreds and thousands binary counters to control the counting thereof and coupled to said prescaler binary counter and said units binary counter to control the selection of the division factor of said prescaler binary cOunter.

Claim 33

A frequency synthesizer according to claim 31, wherein said modulo-M counter, said counter control circuit, said units, tens, hundreds and thousands binary counters and said bistable devices include transistor transistor logic, and said prescaler binary counter includes emitter coupled logic; and further including an emitter coupled logic-to-transistor transistor logic converter coupled to the output of said prescaler binary counter, and a transistor transistor logic-to-emitter coupled logic converter coupled between a control input of said prescaler binary counter and said counter control circuit.