US3854055A
Expired / Lapsed
US
⏱️ 0.0 years remaining
State and sequence detector
Assignee: Bourns Inc
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Filing: 1973-11-29
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Granted: 1974-12-10
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Expires: 1993-11-29
Abstract
Abstract A system is disclosed which permits the sequence of ocurrence of a plurality of events to be monitored and which prevents operation of a machine unless the monitored events occur in a predetermined order. The system of the present invention is particularly suitable for use with any machine or apparatus which operates in a series of discrete or sequential steps, and which is controlled manually in part and automatically in part. The relative state and sequence detector system of the present invention includes a J-K flip-flop circuit for monitoring changes in the operating state of the apparatus, and further includes a logic network for sensing the condition of a plurality of indicators representing the operating states of a plurality of components within the apparatus. The output of the logic network are used to arm the J-K flip-flop and to supply command signals to the automatic control portion of the machine or apparatus.
Inventors
- 👤 J Sparks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:50
CPC Classifications
F; F16; F16P; F16P3/00; F16P3/18; F16P3/20
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
189 words
In a relative state and sequence detector system which includes an apparatus to be controlled, said apparatus designed to undergo repeated operating cycles, and a control means coupled to said apparatus for applying sequential automatic control signals thereto for governing said operating cycles, wherein the improvement comprises the provision of: manually operable switch means coupled to said apparatus and to said control means for actuating said apparatus and for governing the application of said automatic control signals to said apparatus, said manually operable switch means including means for opening and closing a plurality of circuits; and, sequence detector logic means including a logic network coupled to said manually operable switch means and to said control means for stopping said apparatus from continuing said operating cycles unless said plurality of circuits are sequentially closed and opened by operation of said manually operable switch means in a predetermined manner, said sequence detector logic means enabling an uninterrupted application of said sequential automatic control signals to said apparatus in response to said plurality of circuits undergoing a change of state during the interval between a predetermined pair of said automatic control signals.
Claim 2
Dependent Claim
189 words
In a relative state and sequence detector system which includes an apparatus to be controlled, said apparatus designed to undergo repeated operating cycles, and a control means coupled to said apparatus for applying sequential automatic control signals thereto for governing said operating cycles, wherein the improvement comprises the provision of: manually operable switch means coupled to said apparatus and to said control means for actuating said apparatus and for governing the application of said automatic control signals to said apparatus, said manually operable switch means including means for opening and closing a plurality of circuits; and, sequence detector logic means including a logic network coupled to said manually operable switch means and to said control means for stopping said apparatus from continuing said operating cycles unless said plurality of circuits are sequentially closed and opened by operation of said manually operable switch means in a predetermined manner, said sequence detector logic means enabling an uninterrupted application of said sequential automatic control signals to said apparatus in response to said plurality of circuits undergoing a change of state during the interval between a predetermined pair of said automatic control signals.
Claim 3
Dependent Claim
44 words
A relative state and sequence detector system as in claim 1, wherein said sequence detector logic means comprises: memory means for storing automatic control signal information from said control means, and electronic switch means coupled to said memory meAns for controlling the state thereof.
Claim 4
Dependent Claim
20 words
A relative state and sequence detector system as in claim 2, wherein: said memory means includes a J-K flip-flop circuit.
Claim 5
Dependent Claim
53 words
A relative state and sequence detector system as in claim 2, wherein said plurality of circuits include: bistable means coupled to said control means and to said electronic switch means for causing said electronic switch means to change state in response to the generation of a first control signal by said control means.
Claim 6
Dependent Claim
82 words
A relative state and sequence detector system as in claim 4, wherein said bistable means includes: first electromechanical switching means coupled to said control means and responsive to the generation of said first control signal, second electromechanical switching means coupled to said first electormechanical switching means and to both said manually operable switch means and said electronic switch means, said second electromechanical switching means actuated by said first electromechanical switching means provided said manually operable switch means is in its actuated state.
Claim 7
Dependent Claim
100 words
A relative state and sequence detector system as in claim 1, wherein said sequence detector logic means further comprises: first electronic switch means coupled to said manually operable switch means for actuation thereby, first logic gate means coupled to said electronic switch means, said logic gate means changing state upon actuation of said electronic switch means; and said sequence detector logic means is coupled to said control means by circuit means coupled between said logic gate means and said control means for applying an enabling signal to said control means in response to actuation of said manually operable switch means.
Claim 8
Dependent Claim
69 words
A relative state and sequence detector system as in claim 6, wherein said sequence detector logic means further comprises: memory means coupled to said logic gate means for controlling the state of said logic gate means, second logic gate means coupled to said memory means for providing priming signals thereto; and second electronic switch means coupled to said memory means for providing a reset signal to said memory means.
Claim 9
Dependent Claim
126 words
A relative state and sequence detector system as in claim 1, wherein said logic network comprises: triggered flip-flop circuit means having primary, reset, and triggering inputs and having an output, reset circuit means coupled to said reset input for applying a reset signal to said flip-flop circuit means, first electronic switch means coupled to said reset circuit means for controlling the output of said reset circuit means, said first electronic switch means also coupled to said primary input, first logic gate means coupled to said triggering input for applying triggering signals thereto; and second logic gate means coupled to said output of said flip-flop circuit means for providing an output signal from said logic network responsive to the signal present at said flip-flop circuit means output.
Claim 10
Dependent Claim
55 words
A relative state and sequence detector system as in claim 8, wherein said logic network further comprises: third logic gate means coupled to an input of siad second logic gate means for applying an enabling signal thereto; and, second electronic switch means coupled to said third logic gate means for applying an enabling signal thereto.
Claim 11
Dependent Claim
36 words
A relative state and sequence detector system as in claim 8, wherein said logic network further comprises: circuit means coupling an input of said first logic gate means with said output of said flip-flop circuit means.
Claim 12
Dependent Claim
37 words
A relative state and sequence detector system as in claim 9, wherein said logic network further comprises: circuit means coupling an input of said first logic gate means with an input of said third logic gate means.
References Cited (Backward Citations)
US3446985A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-09 | 1978-06-10 | 1978-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-09 | 1982-06-10 | 1982-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-09 | 1986-06-10 | 1986-12-10 | $7700.00 | Window Closed / Lapsed |