US3851330A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Amplitude-to-phase conversion circuit
Assignee: Northrop Grumman Space and Mission Systems Corp
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Filing: 1973-02-20
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Granted: 1974-11-26
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Expires: 1993-02-20
Abstract
Abstract A circuit for converting the angular position of the shaft of a resolver into a phase shift of a carrier wave. Such a conversion circuit may be used for generating a binary number representative of the angle of the resolver shaft. The circuit of the invention requires only a single reactive impedance element which is common to the two adders of the circuit. One of the adders generates a first carrier wave having its phase shifted in one sense while the second adder generates a second carrier wave having its phase shifted in the opposite sense whereby the phase shifts correspond to the angle of the input shaft. Errors due to drift of the components of the network interconnecting the resolver with the adders are minimized because only a single reactive impedance element is used which is common to the two adders. Accordingly, the errors due to drift of the reactive impedance element are reduced by at least one order of magnitude over those of known circuits.
Inventors
- 👤 W Huber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:57
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/64; H03M1/645
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
329 words
An amplitude-to-phase conversion circuit comprising: a carrier frequency source; a resolver having an analog input shaft and a transformer having input and output terminals, said input terminals being coupled to said carrier source, a first output terminal producing a first output signal having an amplitude proportional to the sine of the angle of said analog shaft, and a second output terminal producing a second output signal having an amplitude proportional to the cosine of said shaft angle; a first adder having two input terminals; a second adder having two input terminals; a purely resistive network interconnecting each of said resolver outputs with each of said input terminals of said adders; and a single phase shifting network connected between said first output terminal of said resolver and one input terminal of each of said adders, said phase shifting network including one resistor and a single reactive impedance element for shifting the phase of said first output signal substantially by 45*; said networks being so connected as to apply said second signal to said first adder, to apply said first signal shifted in phase by said phase shifting network to said first adder, And means including said adder to apply the negative of said first signal to said first adder, said networks being further so connected as to apply said second signal to said second adder, said first signal to said second adder, and means including said second adder to apply the negative of said phase-shifted first signal to said second adder, said networks and said adders being so arranged that said first adder generates a first resultant signal having a phase shifted in one sense with respect to the phase of said carrier source while said second adder generates a second resultant signal having a phase shifted in the opposite sense, said phase shifts corresponding to the angle of said input shaft, whereby undesired variations of the resultant signals due to variations of said reactive impedance element are substantially compensated.
Claim 2
Dependent Claim
329 words
An amplitude-to-phase conversion circuit comprising: a carrier frequency source; a resolver having an analog input shaft and a transformer having input and output terminals, said input terminals being coupled to said carrier source, a first output terminal producing a first output signal having an amplitude proportional to the sine of the angle of said analog shaft, and a second output terminal producing a second output signal having an amplitude proportional to the cosine of said shaft angle; a first adder having two input terminals; a second adder having two input terminals; a purely resistive network interconnecting each of said resolver outputs with each of said input terminals of said adders; and a single phase shifting network connected between said first output terminal of said resolver and one input terminal of each of said adders, said phase shifting network including one resistor and a single reactive impedance element for shifting the phase of said first output signal substantially by 45*; said networks being so connected as to apply said second signal to said first adder, to apply said first signal shifted in phase by said phase shifting network to said first adder, And means including said adder to apply the negative of said first signal to said first adder, said networks being further so connected as to apply said second signal to said second adder, said first signal to said second adder, and means including said second adder to apply the negative of said phase-shifted first signal to said second adder, said networks and said adders being so arranged that said first adder generates a first resultant signal having a phase shifted in one sense with respect to the phase of said carrier source while said second adder generates a second resultant signal having a phase shifted in the opposite sense, said phase shifts corresponding to the angle of said input shaft, whereby undesired variations of the resultant signals due to variations of said reactive impedance element are substantially compensated.
Claim 3
Dependent Claim
16 words
A conversion circuit as defined in claim 1 wherein said reactive impedance element is a capacitor.
Claim 4
Dependent Claim
16 words
A conversion circuit as defined in claim 1 wherein said reactive impedance element is an inductor.
Claim 5
Dependent Claim
271 words
An amplitude-to-phase conversion circuit comprising: a carrier frequency source; a resolver having an analog input shaft and a transformer having input and output terminals, said input terminals being coupled to said carrier frequency source, a first output terminal generating a first output signal having amplitudes proportional to the sine of the angle of said input shaft, and a second output terminal generating a second output signal having amplitudes proportional to the cosine of said input shaft angle; a first adder having two input terminals; a second adder having two input terminals; a first resistor connecting said first output terminal to a first input terminal of said first adder; means coupled to said first resistor and including said transformer and said first adder for impressing the negative of said first output signal on said first adder; a second resistor connecting said second output terminal to said first input terminal of said first adder; a reactive impedance element and a third resistor connected in series between said first output terminal and the second input terminal of said first adder; a fourth resistor connected between said first output terminal and a first input terminal of said second adder; a fifth resistor connecting said second output terminal to said first input terminal of said second adder; a sixth resistor connecting the second input terminal of said first adder to the first input terminal of said second adder; and means coupled to said sixth resistor and including said transformer and said second adder for impressing the negative of the signal shifted in phase by said reactive impedance element and said third resistor onto said second adder.
Claim 6
Dependent Claim
271 words
An amplitude-to-phase conversion circuit comprising: a carrier frequency source; a resolver having an analog input shaft and a transformer having input and output terminals, said input terminals being coupled to said carrier frequency source, a first output terminal generating a first output signal having amplitudes proportional to the sine of the angle of said input shaft, and a second output terminal generating a second output signal having amplitudes proportional to the cosine of said input shaft angle; a first adder having two input terminals; a second adder having two input terminals; a first resistor connecting said first output terminal to a first input terminal of said first adder; means coupled to said first resistor and including said transformer and said first adder for impressing the negative of said first output signal on said first adder; a second resistor connecting said second output terminal to said first input terminal of said first adder; a reactive impedance element and a third resistor connected in series between said first output terminal and the second input terminal of said first adder; a fourth resistor connected between said first output terminal and a first input terminal of said second adder; a fifth resistor connecting said second output terminal to said first input terminal of said second adder; a sixth resistor connecting the second input terminal of said first adder to the first input terminal of said second adder; and means coupled to said sixth resistor and including said transformer and said second adder for impressing the negative of the signal shifted in phase by said reactive impedance element and said third resistor onto said second adder.
Claim 7
Dependent Claim
16 words
A conversion circuit as defined in claim 4 wherein said reactive impedance element is a capacitor.
Claim 8
Dependent Claim
16 words
A conversion circuit as defined in claim 4 wherein said reactive impedance element is an inductor.
Claim 9
Dependent Claim
85 words
A conversion circuit as defined in claim 5 wherein the resistance of said first resistor equals that of said second resistor, wherein the resistance of said third resistor is one half of that of said sixth resistor, wherein the resistance of said fourth resistor equals that of said fifth resistor and equals six times that of said third resistor, and wherein the admittance of said capacitor at said carrier frequency multiplied by the sum of the resistance of said third and sixth resistors equals unity.
Claim 10
Dependent Claim
82 words
A conversion circuit as defined in claim 7 wherein said first adder has a seventh resistor connected between its first input and its output terminals to provide a feedback path, and wherein said second adder has an eighth resistor connected between its first input and its output terminals to provide a feedback path, the resistance of said seventh resistor being equal to that of said first resistor and the resistance of said eighth resistor being equal to that of said fifth resistor.
Claim 11
Dependent Claim
81 words
A conversion circuit as defined in claim 6 wherein the resistance of said first and second resistors is equal, wherein the resistance of said third resistor is one half of that of said sixth resistor, wherein the resistance of said fourth resistor equals that of said fifth resistor and equals six times that of said third resistor, and wherein the admittance of said inductor at said carrier frequency multiplied by the combined resistances of said third and sixth resistors equals unity.
Claim 12
Dependent Claim
82 words
A conversion circuit as defined in claim 9 wherein said first adder has a seventh resistor connected between its first input and its output terminals to provide a feedback path, and wherein said second adder has an eighth resistor connected between its first input and its out terminals to provide a feedback path, the resistance of said seventh resistor being equal to that of said first resistor and the resistance of said eighth resistor being equal to that of said fifth resistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-25 | 1978-05-27 | 1978-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-25 | 1982-05-27 | 1982-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-25 | 1986-05-27 | 1986-11-26 | $7700.00 | Window Closed / Lapsed |