Method of assembling semiconductor devices

Claim 1

A method of assembling the leads of a plurality of transistors into apertures of an associated insulating pad which comprises a. supporting a plurality of transistors within apertures of a first supporting member and the leads extending in an outward direction; b. confining said transistors in a vertical direction; c. inverting said supported and confined transistors; d. positioning a plurality of insulating pads having apertures in counter-sunk apertures of a second supporting member; e. positioning the inverted confined transistors over the counter-sunk apertures of said second supporting member; f. releasing the confined transistor to drop vertically into engagement with said insulating pads; and g. agitating both first and second support members to position the leads of said transistor through the apertures of the insulating pads to the bottom of said counter-sunk apertures.

Claim 2

A method of assembling the leads of a plurality of transistors into apertures of an associated insulating pad which comprises a. supporting a plurality of transistors within apertures of a first supporting member and the leads extending in an outward direction; b. confining said transistors in a vertical direction; c. inverting said supported and confined transistors; d. positioning a plurality of insulating pads having apertures in counter-sunk apertures of a second supporting member; e. positioning the inverted confined transistors over the counter-sunk apertures of said second supporting member; f. releasing the confined transistor to drop vertically into engagement with said insulating pads; and g. agitating both first and second support members to position the leads of said transistor through the apertures of the insulating pads to the bottom of said counter-sunk apertures.

Claim 3

A method of assembling the leads of a plurality of transistors into apertures of an associated insulating pad which comprises a. supporting a plurality of transistors within apertures of a first supporting member and the leads extending in an outward direction; b. confining said transistors in a vertical direction; c. inverting said supported and confined transistors; d. positioning a plurality of insulating pads having apertures in counter-sunk apertures of a second supporting member; e. positioning the inverted confined transistors over the counter-sunk apertures of said second supporting member; f. releasing the confined transistors to drop vertically into engagement with said insulating pads; and g. agitating both first and second support members to position the leads of said transistors in the apertures of the insulating pads.

Claim 4

A method of assembling the leads of a plurality of transistors into apertures of an associated insulating pad which comprises a. supporting a plurality of transistors within apertures of a first supporting member and the leads extending in an outward direction; b. confining said transistors in a vertical direction; c. inverting said supported and confined transistors; d. positioning a plurality of insulating pads having apertures in counter-sunk apertures of a second supporting member; e. positioning the inverted confined transistors over the counter-sunk apertures of said second supporting member; f. releasing the confined transistors to drop vertically into engagement with said insulating pads; and g. agitating both first and second support members to position the leads of said transistors in the apertures of the insulating pads.

Claim 5

A method of assembling transistors into an associated insulating pad where each transistor comprises a flanged body portion with leads depending therefrom and the insulating pad containing apertures through which the leads are to extend, which comprises a. positioning the transistors into apertures of a first support plate with leads extending outwardly; b. positioning a second apertured plate on said first plate with the leads of the transistors located within the apertures of said second plate; c. removing said first plate after inverting said first and second plates; d. positioning a third apertured plate on said second plate; e. inverting said second and third plates to drop the transistors into the apertures of the third plate with the body portion and the leads of the transistors positioned within the apertures; f. removing said second plate; g. sliding a blocking plate over the apertures of said third plate; h. positioning a plurality of insulating pads into apertures of a fourth apertured plate; i. inverting said third plate; j. positioning said third plate on said fourth plate; k. removing said blocking plate; and l. vibrating said third and fourth plates to drop the leads of the transistors through the apertures in the insulating pads.

Claim 6

A method of assembling transistors into an associated insulating pad where each transistor comprises a flanged body portion with leads depending therefrom and the insulating pad containing apertures through which the leads are to extend, which comprises a. positioning the transistors into apertures of a first support plate with leads extending outwardly; b. positioning a second apertured plate on said first plate with the leads of the transistors located within the apertures of said second plate; c. removing said first plate after inverting said first and second plates; d. positioning a third apertured plate on said second plate; e. inverting said second and third plates to drop the transistors into the apertures of the third plate with the body portion and the leads of the transistors positioned within the apertures; f. removing said second plate; g. sliding a blocking plate over the apertures of said third plate; h. positioning a plurality of insulating pads into apertures of a fourth apertured plate; i. inverting said third plate; j. positioning said third plate on said fourth plate; k. removing said blocking plate; and l. vibrating said third and fourth plates to drop the leads of the transistors through the apertures in the insulating pads.

Claim 8

A method of assembling transistors into an associated insulating pad where each transistor comprises a flanged body portion with leads depending therefrom and the insulating pads having apertures orientated with the location of the leads of the transistors which comprises a. vibrating a plurality of transistors into counter-sunk apertures of a first apertured plate with leads extending outwardly from said plate; b. positioning a second plate having apertures narrower than the flanges of the transistors, on said first plate with the leads of the transistors located within the apertures of said second plate; c. inverting said first and second plates; d. removing said first plate; e. positioning a third plate having counter-sunk apertures on said second plate and over said transistors, the counter-sunk portion of the apertures having a greater depth than the length of the leads of said transistors; f. inverting said second and third plates thereby dropping the transistors into the counter-sunk apertures of said third plate; g. removing said second plate; h. mounting a blocking plate on said third plate to confine the transistors in said counter-sunk apertures; i. vibrating a plurality of insulating pads into counter-sunk apertures of a fourth plate, the pads being located in the counter-sunk portions of the apertures; j. inverting said third plate; k. positioning said third plate on said fourth plate; l. removing said blocking plate from said third plate; m. and vibrating said third and fourth plates to drop the leads of the transistors through the apertures in the insulating pads.

Claim 9

A method of assembling transistors into an associated insulating pad where each transistor comprises a flanged body portion with leads depending therefrom and the insulating pads having apertures orientated with the location of the leads of the transistors which comprises a. vibrating a plurality of transistors into counter-sunk apertures of a first apertured plate with leads extending outwardly from said plate; b. positioning a second plate having apertures narrower than the flanges of the transistors, on said first plate with the leads of the transistors located within the apertures of said second plate; c. inverting said first and second plates; d. removing said first plate; e. positioning a third plate having counter-sunk apertures on said second plate and over said transistors, the counter-sunk portion of the apertures having a greater depth than the length of the leads of said transistors; f. inverting said second and third plates thereby dropping the transistors into the counter-sunk apertures of said third plate; g. removing said second plate; h. mounting a blocking plate on said third plate to confine the transistors in said counter-sunk apertures; i. vibrating a plurality of insulating pads into counter-sunk apertures of a fourth plate, the pads being located in the counter-sunk portions of the apertures; j. inverting said third plate; k. positioning said third plate on said fourth plate; l. removing said blocking plate from said third plate; m. and vibrating said third and fourth plates to drop the leads of the transistors through the apertures in the insulating pads.