US3849767A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory circuit
Assignee: NEC Corp
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Filing: 1973-10-23
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Granted: 1974-11-19
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Expires: 1993-10-23
Abstract
Abstract A semiconductor memory including a matrix array of storage cells employs read and write word lines oriented along one matrix axis, and common digit lines disposed about the other matrix axis. Each storage cell comprises three interconnected read, write and information retaining insulated gate field effect transistors, information being preserved via stray capacitance at the gate of the information preserving transistor. In accordance with varying aspects of the present invention, information is read out from each storage cell in the same polarity as it is stored therein, and each memory cell is refreshed in phase, thus permitting overall system simplifications. In addition, information refreshing and input/output gating circuitry is employed.
Inventors
- 👤 H Shirato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:24
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/403; G11C11/405; G11C11/406
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
333 words
A memory circuit having memory cells arranged in matrix form, a ''''read'''' word line and a ''''write'''' word line provided at each row of said matrix, a common digit line provided at each column of said matrix, and a power supply, each of said memory cells comprising first, second and third insulated-gate field effect transistors each having a control terminal, an input terminal and an output terminal, said output terminal of said first insulatedgate field effect transistor and said input terminal of said second insulated-gate field effect transistor being connected to said common digit line at the matrix column where said memory cell is located, said input terminal of said first insulated-gate field effect transistor being connected to one of said input and output terminals of said third insulated-gate field effect transistor, said control terminal of said first insulated-gate field effect transistor being connected to said ''''read'''' word line of the row with which said memory cell is associated, said output terminal of said second insulated-gate field effect transistor being connected to said control terminal of said third insulated-gate field effect transistor, said control terminal of said second insulated-gate field effect transistor being connected to said ''''write'''' word line at said row with which said memory cell is associated, the other of said input and output terminals of said third insulated-gate field effect transistor being connected to one terminal of said power supply, means connecting each of said common digit lines to the other terminal of said power supply, said one terminal of said power supply having a potential capable of rendering said insulated-gate field effect transistor conductive when applied to the control terminal thereof, wherein after said each common digit line is connected to said other terminal of said power supply and is subsequently disconnected therefrom, at least one of said ''''read'''' word lines is selected an information in phase with information stored in said memory cell coupled to the selected ''''read'''' word line is read out to said common digit line.
Claim 2
Dependent Claim
333 words
A memory circuit having memory cells arranged in matrix form, a ''''read'''' word line and a ''''write'''' word line provided at each row of said matrix, a common digit line provided at each column of said matrix, and a power supply, each of said memory cells comprising first, second and third insulated-gate field effect transistors each having a control terminal, an input terminal and an output terminal, said output terminal of said first insulatedgate field effect transistor and said input terminal of said second insulated-gate field effect transistor being connected to said common digit line at the matrix column where said memory cell is located, said input terminal of said first insulated-gate field effect transistor being connected to one of said input and output terminals of said third insulated-gate field effect transistor, said control terminal of said first insulated-gate field effect transistor being connected to said ''''read'''' word line of the row with which said memory cell is associated, said output terminal of said second insulated-gate field effect transistor being connected to said control terminal of said third insulated-gate field effect transistor, said control terminal of said second insulated-gate field effect transistor being connected to said ''''write'''' word line at said row with which said memory cell is associated, the other of said input and output terminals of said third insulated-gate field effect transistor being connected to one terminal of said power supply, means connecting each of said common digit lines to the other terminal of said power supply, said one terminal of said power supply having a potential capable of rendering said insulated-gate field effect transistor conductive when applied to the control terminal thereof, wherein after said each common digit line is connected to said other terminal of said power supply and is subsequently disconnected therefrom, at least one of said ''''read'''' word lines is selected an information in phase with information stored in said memory cell coupled to the selected ''''read'''' word line is read out to said common digit line.
Claim 3
Dependent Claim
32 words
The memory circuit of claim 1, in which said insulated-gate field effect transistors are of the N-channel type, said one terminal of said power supply being characterized by a relatively high potential.
Claim 4
Dependent Claim
33 words
The memory cell circuit of claim 1, in which said insulated-gate field effect transistors are of the P-channel type, said one terminal of said power supply being characterized by a relatively low potential.
Claim 5
Dependent Claim
220 words
The memory circuit according to claim 1, further comprising a level refreshing circuit arranged at each matrix column and having first and second control terminals, an input terminal, and an output terminal, said input and output terminals of said level refreshing circuit being connected to said common digit line at the column with which said level refreshing circuit is associated, said first control terminal of said level refreshing circuit being connected to source means for supplying a first signal signifying the external read and write operational mode for said memory cell, said second control terminal of said level refreshing circuit being connected to source means for supplying a second signal signifying the selecting operation for said ''''write'''' word lines, wherein said level refreshing circuit does not operate when said second signal is not supplied to said second control terminal of said level refreshing circuit, while when said second signal is supplied to said second control terminal of said level refreshing circuit and said first signal is not supplied to said first control terminal of said level refreshing circuit, said level refreshing circuit amplifies said information of said common digit line as supplied from said input terminal of said level refreshing circuit and delivers the amplified information to said common digit line from said output terminal of said level refreshing circuit.
Claim 6
Dependent Claim
312 words
A mEmory circuit having memory cells arranged in matrix form, a ''''read'''' word line and a ''''write'''' word line provided at each row of said matrix, a common digit line provided at each column of said matrix, and a power supply, each of said memory cells comprising first, second and third insulated-gate field effect transistors, each having a control terminal, an input terminal and an output terminal, said output terminal of said first insulated-gate field effect transistor and said input terminal of said second insulated-gate field effect transistor being connected to said common digit line at the matrix column where said memory cell is located, said input terminal of said first insulated-gate field effect transistor being connected to one of said input and output terminals of said third insulated-gate field effect transistor, said control terminal of said first insulated-gate field effect transistor being connected to said ''''read'''' word line of the row with which said memory cell is associated, said output terminal of said second insulated-gate field effect transistor being connected to said control terminal of said third insulated-gate field effect transitor, said control terminal of said second insulated-gate field effect transistor being connected to said ''''write'''' word line at said row with which said memory cell is associated, the other of said input and output terminals of said third insulated-gate field effect transistor being connected to one terminal of said power supply, means connecting each of said common digit lines to the other terminal of said power supply, said one terminal of said power supply having a potential capable of rendering said insulated-gate field effect transistor conductive when applied to the control terminal thereof, further comprising switching means for selectively connecting each of said common digit lines to said other terminal of said power supply, and means for supplying a memory interrogating signal to at least one of said read lines.
Claim 7
Dependent Claim
312 words
A mEmory circuit having memory cells arranged in matrix form, a ''''read'''' word line and a ''''write'''' word line provided at each row of said matrix, a common digit line provided at each column of said matrix, and a power supply, each of said memory cells comprising first, second and third insulated-gate field effect transistors, each having a control terminal, an input terminal and an output terminal, said output terminal of said first insulated-gate field effect transistor and said input terminal of said second insulated-gate field effect transistor being connected to said common digit line at the matrix column where said memory cell is located, said input terminal of said first insulated-gate field effect transistor being connected to one of said input and output terminals of said third insulated-gate field effect transistor, said control terminal of said first insulated-gate field effect transistor being connected to said ''''read'''' word line of the row with which said memory cell is associated, said output terminal of said second insulated-gate field effect transistor being connected to said control terminal of said third insulated-gate field effect transitor, said control terminal of said second insulated-gate field effect transistor being connected to said ''''write'''' word line at said row with which said memory cell is associated, the other of said input and output terminals of said third insulated-gate field effect transistor being connected to one terminal of said power supply, means connecting each of said common digit lines to the other terminal of said power supply, said one terminal of said power supply having a potential capable of rendering said insulated-gate field effect transistor conductive when applied to the control terminal thereof, further comprising switching means for selectively connecting each of said common digit lines to said other terminal of said power supply, and means for supplying a memory interrogating signal to at least one of said read lines.
References Cited (Backward Citations)
US3796998A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-18 | 1978-05-20 | 1978-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-18 | 1982-05-20 | 1982-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-18 | 1986-05-20 | 1986-11-19 | $7700.00 | Window Closed / Lapsed |