Signal comparator circuit for analog control systems

Claim 2

A differential amplifier for comparing first and second input signals each of which is variable in amplitude and polarity and providing output signAls which indicate amplitude and polarity differences between the compared signals, said amplifier comprising an input stage with a first input transistor having a first control electrode, and a first output electrode, and a second input transistor having a second control electrode, and a second output electrode, first means for extending to said first control electrode a first input signal which is variable in amplitude and polarity at said first control electrode, second means for extending to said second control electrode a second input signal which is variable in amplitude and polarity at said second control electrode, bias means biasing said first and second input transistors to be normally conducting for amplifying said first and second variable input signals to provide amplified signals at said first and second output electrodes, respectively, said bias means including a constant current source for supplying a constant current to said first and second input transistors such that said amplified signals provided by said input transistors establish a potential difference of one polarity between the first and second output electrodes whenever the input signal extended to the control electrode of one of said input transistors increases relative to the input signal extended to the control electrode of the other input transistor and a potential difference of the opposite polarity whenever the input signal extended to the control electrode of said one input transistor decreases relative to the input signal extended to the control electrode of the other input transistor, and an output stage including a first switching transistor having first and second input electrodes connected to said first and second output electrodes, respectively, and a second switching transistor having first and second input electrodes connected to said second and first output electrodes, respectively, and means normally reverse biasing said first and second switching transistors, one of said switching transistors becoming forward biased to provide a first output signal whenever one of said input signals increases a predetermined amount relative to the other one of said input signals such that the amplitude of the amplified signal provided at said first output electrode is a given amount greater than the amplitude of the amplified signal provided at said second output electrode, and the other one of said switching transistors becoming forward biased to provide a second output signal whenever said one input signal decreases said predetermined amount relative to said other input signal such that the amplitude of the amplified signal provided at said second output electrode is a given amount greater than the amplitude of the amplified signal provided at said first output electrode.

Claim 3

A differential amplifier as set forth in claim 1 wherein said first and second input electrodes of said first and second switching transistors comprise emitter and base electrodes, respectively, of said switching transistors, and wherein said first and second output signals are provided at collector electrodes of said first and second switching transistors, respectively.

Claim 4

A differential amplifier as set forth in claim 2 including first output switching means having a gate electrode connected to the collector electrode of said first switching transistor and controlled by said first output signal to enable said first output switching means, and second output switching means having a gate electrode connected to the collector electrode of said second switching transistor and controlled by said second output signal to enable said second output switching means.

Claim 5

A differential amplifier as set forth in claim 1 wherein said first and second output electrodes comprise collector electrodes of said input transistors, said which and second control electrodes comprise base electrodes for receiving variable input signals, and said first and second input transistors further include first and second emitter electrodes, respectiVely, commonly connected to said constant current source. the collectors at the second

Claim 6

A differential amplifier for comparing first and second input signals and providing output signals which indicate amplitude and polarity differences between the compared signals, said amplifier comprising an input stage with a first input transistor having a first control electrode connected to receive said first input signal, and a first output electrode, and a second input transistor having a second control electrode connected to receive said second input signal, and a second output electrode, means biasing said first and second input transistors to be normally conducting for amplifying said first and second input signals to provide amplified signals at said first and second output electrodes, respectively, and an output stage including a first switching transistor having a base electrode connected to said second output electrode and an emitter electrode, and a second switching transistor having a base electrode connected to said first output electrode and an emitter electrode, a first drive transistor having a base-emitter circuit connected between the first output electrode and the emitter electrode of said first switching transistor, and a second drive transistor having a base-emitter circuit connected between said second output electrode and the emitter electrode of said second switching transistor, and means normally reverse biasing said first and second switching transistors, one of said switching transistors becoming forward biased to provide a first output signal at a collector electrode thereof whenever one of said input signals increases a predetermined amount relative to the other one of said input signals such that the amplitude of the amplified signal provided at said first output electrode is a given amount greater than the amplitude of the amplified signal provided at said second output electrode, and the other one of said switching transistors becoming forward biased to provide a second output signal at a collector electrode thereof whenever said one input signal decreases said predetermined amount relative to said other input signal such that the amplitude of the amplified signal provided at said second output electrode is a given amount greater than the amplitude of the amplified signal provided at said first output electrode.

Claim 7

A differential amplifier for comparing first and second input signals and providing output signals which indicate amplitude and polarity differences between the compared signals, said amplifier comprising an input stage with a first input transistor having a first control electrode connected to receive said first input signal, and a first output electrode, and a second input transistor having a second control electrode connected to receive said second input signal, and a second output electrode, means biasing said first and second input transistors to be normally conducting for amplifying said first and second input signals to provide amplified signals at said first and second output electrodes, respectively, and an output stage including a first switching transistor having a base electrode connected to said second output electrode and an emitter electrode, and a second switching transistor having a base electrode connected to said first output electrode and an emitter electrode, a first drive transistor having a base-emitter circuit connected between the first output electrode and the emitter electrode of said first switching transistor, and a second drive transistor having a base-emitter circuit connected between said second output electrode and the emitter electrode of said second switching transistor, and means normally reverse biasing said first and second switching transistors, one of said switching transistors becoming forward biased to provide a first output signal at a collector electrode thereof whenever one of said input signals increases a predetermined amount relative to the other one of said input signals such that the amplitude of the amplified signal provided at said first output electrode is a given amount greater than the amplitude of the amplified signal provided at said second output electrode, and the other one of said switching transistors becoming forward biased to provide a second output signal at a collector electrode thereof whenever said one input signal decreases said predetermined amount relative to said other input signal such that the amplitude of the amplified signal provided at said second output electrode is a given amount greater than the amplitude of the amplified signal provided at said first output electrode.

Claim 8

A differential amplifier for comparing first and second input signals each of which is variable in amplitude and polarity and indicate amplitude providing output signals which indicateamplitude and polarity differences between the compared signals, said amplifier comprising an input stage with first and second input transistors each having an emitter, a base, and a collector, said emitters being commonly connected to constant current source, first means for providing a first input signal which is variable in amplitude and polarity at the base of said first input transistor, second means for providing a second input signal which is variable in amplitude and polarity at the base of said second input transistor, said constant current source extending a constant current to the bases of said first and second input transistors to enable a potential difference of one polarity to be established between the collectors of said first and second input transistors whenever the input signal provided at the base of one of said input transistors increases relative to the input signal provided at the base of the other input transistor, and a potential difference of the opposite polarity to be established between the collectors of said first and second input transistors whenever the input signal provided at the base of said one input transistor decreases relative to the input signal provided at the base of the other input transistor, and an output stage including first and second switching transistors each having an emitter, a base, and a collector, the emitter and the base of the first switching transistor being connected to the collectors of said firsT and second input transistors, respectively, and the emitter and the base of the second switching transistor being connected to the collectors of the second and first input transistors, respectively, and means normally reverse biasing said first and second switching transistors, said first switching transistor becoming forward biased and said second switching transistor remaining reverse biased to provide a first output signal whenever the input signal provided at the base of said first input transistor increases by at least a given amount relative to the input signal provided at the base of the second input transistor, and said first switching transistor remaining reverse biased and said second switching transistor becoming forward biased to provide a second output signal whenever said input signal provided at the base of the first input transistor decreases by at least said given amount relative to the input signal provided at the base of said second input transistor.

Claim 9

A differential amplifier for comparing first and second input signals each of which is variable in amplitude and polarity and indicate amplitude providing output signals which indicateamplitude and polarity differences between the compared signals, said amplifier comprising an input stage with first and second input transistors each having an emitter, a base, and a collector, said emitters being commonly connected to constant current source, first means for providing a first input signal which is variable in amplitude and polarity at the base of said first input transistor, second means for providing a second input signal which is variable in amplitude and polarity at the base of said second input transistor, said constant current source extending a constant current to the bases of said first and second input transistors to enable a potential difference of one polarity to be established between the collectors of said first and second input transistors whenever the input signal provided at the base of one of said input transistors increases relative to the input signal provided at the base of the other input transistor, and a potential difference of the opposite polarity to be established between the collectors of said first and second input transistors whenever the input signal provided at the base of said one input transistor decreases relative to the input signal provided at the base of the other input transistor, and an output stage including first and second switching transistors each having an emitter, a base, and a collector, the emitter and the base of the first switching transistor being connected to the collectors of said firsT and second input transistors, respectively, and the emitter and the base of the second switching transistor being connected to the collectors of the second and first input transistors, respectively, and means normally reverse biasing said first and second switching transistors, said first switching transistor becoming forward biased and said second switching transistor remaining reverse biased to provide a first output signal whenever the input signal provided at the base of said first input transistor increases by at least a given amount relative to the input signal provided at the base of the second input transistor, and said first switching transistor remaining reverse biased and said second switching transistor becoming forward biased to provide a second output signal whenever said input signal provided at the base of the first input transistor decreases by at least said given amount relative to the input signal provided at the base of said second input transistor.

Claim 10

A differential amplifier for comparing first and second input signals each of which is variable in amplitude and polarity and providing output signals which indicate amplitude and polarity differences between the compared signals, said amplifier comprising an input stage with a first input transistor having a first control electrode, and a first output electrode, and a second input transistor having a second control electrode, and a second output electrode, first means for extending to said first control electrode a first input signal which is variable in amplitude and polarity at said first control electrode, second means for extending to said second control electrode a second input signal which is variable in amplitude and polarity at said second control electrode, bias means for biasing said first and second input transistors to be normally conducting for amplifying said first and second variable input signals to provide amplified signals at said first and second output electrodes, respectively, said bias means including a constant current source for supplying a constant current to said first and second input transistors such that said amplified signals provided by said input transistors establish a potential difference of one polarity between the first and second output electrodes whenever the input signal extended to the control electrode of one of said input transistor increases relative to the input signal extended to the control electrode of the other input transistor and a potential difference of the opposite polarity whenever the input signal extended to the control electrode of said one input transistor decreases relative to the input signal extended to the control electrode of the other input transistor, and an output stage including a first switching transistor having first and second input electrodes connected to said first and second output electrodes, respectively, and a second switching transistor having first and second input electrodes connected to said second and first output electrodes, resepctively, and means normally biasing said first and second switching transistors to a first conductive state, one of said switching transistors becoming biased to a second conductive state to provide a first output signal whenever one of said input signals increases a predetermined amount relative to the other one of said input signals such that the amplitude of the amplified signal provided at said first output electrode is a given amount greater than the amplitude of the amplified signal provided at said second output electrode, and the other switching transistor becoming biased to said second conductive state to provide a second output signal whenever said one input signal decreases said predetermined amount relative to said other input signal such that the amplitude of the amplified signal provided at said second output electrode is a given amount greater than the amplitude of the amplified signal provided at said first output electrode.

Claim 11

A differential amplifier for comparing first and second input signals each of which is variable in amplitude and polarity and providing output signals which indicate amplitude and polarity differences between the compared signals, said amplifier comprising an input stage with a first input transistor having a first control electrode, and a first output electrode, and a second input transistor having a second control electrode, and a second output electrode, first means for extending to said first control electrode a first input signal which is variable in amplitude and polarity at said first control electrode, second means for extending to said second control electrode a second input signal which is variable in amplitude and polarity at said second control electrode, bias means for biasing said first and second input transistors to be normally conducting for amplifying said first and second variable input signals to provide amplified signals at said first and second output electrodes, respectively, said bias means including a constant current source for supplying a constant current to said first and second input transistors such that said amplified signals provided by said input transistors establish a potential difference of one polarity between the first and second output electrodes whenever the input signal extended to the control electrode of one of said input transistor increases relative to the input signal extended to the control electrode of the other input transistor and a potential difference of the opposite polarity whenever the input signal extended to the control electrode of said one input transistor decreases relative to the input signal extended to the control electrode of the other input transistor, and an output stage including a first switching transistor having first and second input electrodes connected to said first and second output electrodes, respectively, and a second switching transistor having first and second input electrodes connected to said second and first output electrodes, resepctively, and means normally biasing said first and second switching transistors to a first conductive state, one of said switching transistors becoming biased to a second conductive state to provide a first output signal whenever one of said input signals increases a predetermined amount relative to the other one of said input signals such that the amplitude of the amplified signal provided at said first output electrode is a given amount greater than the amplitude of the amplified signal provided at said second output electrode, and the other switching transistor becoming biased to said second conductive state to provide a second output signal whenever said one input signal decreases said predetermined amount relative to said other input signal such that the amplitude of the amplified signal provided at said second output electrode is a given amount greater than the amplitude of the amplified signal provided at said first output electrode.