US3849672A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital data transmission system
Assignee: Raytheon Co
•
Filing: 1972-06-30
•
Granted: 1974-11-19
•
Expires: 1992-06-30
Abstract
Abstract A digital data transmission system wherein a plurality of input/output devices are interconnected through a transmission line. Such system includes a transistor, biased in its inverted mode of operation and disposed to shunt a matching impedance connected across the transmission line thereby to improve noise immunity in the system.
Inventors
- 👤 C Georgopoulos
- 👤 C Ross
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:11
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/40; H04L12/40006; H04L12/40032
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
118 words
In a digital data transmission system, the combination comprising: a. a transmission line; b. an input device; c. an output device, the input device and the output device being interconnected through the transmission line; d. an impedance matching network terminating such transmission line, such network comprising: i. electrical means having an impedance, such impedance being matched to the impedance of the transmission line; ii. a transistor, the collector electrode and the emitter electrode thereof being connected in shunt across the electrical means, such transistor being constructed to have a normal current gain at least ten times as large as the inverse gain of said transistor; and iii. means for biasing such transistor in its inverse mode of operation.
Claim 2
Dependent Claim
118 words
In a digital data transmission system, the combination comprising: a. a transmission line; b. an input device; c. an output device, the input device and the output device being interconnected through the transmission line; d. an impedance matching network terminating such transmission line, such network comprising: i. electrical means having an impedance, such impedance being matched to the impedance of the transmission line; ii. a transistor, the collector electrode and the emitter electrode thereof being connected in shunt across the electrical means, such transistor being constructed to have a normal current gain at least ten times as large as the inverse gain of said transistor; and iii. means for biasing such transistor in its inverse mode of operation.
Claim 3
Dependent Claim
44 words
The combination recited in claim 1 wherein the electrical means is a resistor having a pair of terminals and the collector electrode and the emitter electrode of the transistor are connected directly to a respective one of the pair of terminals of the resistor.
References Cited (Backward Citations)
US3302035A
Cited
US3705418A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-18 | 1978-05-20 | 1978-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-18 | 1982-05-20 | 1982-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-18 | 1986-05-20 | 1986-11-19 | $7700.00 | Window Closed / Lapsed |