US3846712A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Differential amplifier with dynamic biasing
Assignee: AT&T Inc
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Filing: 1973-03-12
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Granted: 1974-11-05
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Expires: 1993-03-12
Abstract
Abstract The differential amplifier current folder and coder circuit of the present invention is dynamically biased in accordance with the magnitude of the input signal to the differential amplifier. The biasing current through the main coding paths of the folder circuitry is thus reduced for lower magnitude input signals, and the coding error introduced due to resistor variations (i.e., I Delta R voltage drops) and transistor base currents varies in accordance with the magnitude of the input signal rather than remaining a constant due to the presence of a constant biasing current. Lower magnitude input signals can thus be coded with a minimum of error using either thin film techniques or components readily available from commercial sources.
Inventors
- 👤 F Kiko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:17
CPC Classifications
H; H03; H03G; H03G1/00; H03G1/0005; H03G1/0035; H03G1/0082; H03F; H03F3/00; H03F3/45; H03F3/45071; H03G1/0017; H03G1/0023; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/42
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
263 words
A dynamically biased amplifier comprising first and second transistors, d.c. biasing means connected to the base and emitter electrodes of each of said first and second transistors to bias said first and second transistors for operation as a differential amplifier, an input signal to be differentially amplified connected to the base electrode of said first transistor, a third transistor, a source of biasing current for maintaining a constant current therethrough, means connecting the collectoremitter paths of said first and second transistors in parallel, means serially connecting the parallel combination of the collector-emitter paths of said first and second transistors, the collector-emitter path of said third transistor, and said source of constant biasing current, a fourth transistor having its collector-emitter path connected across said source of biasing current to provide an alternate current path for a portion of the constant current maintained by said source of biasing current and means connecting said input signal to the base electrode of said third transistor and to the base electrode of said fourth transistor to vary the biasing current flow through the parallel collector-emitter paths of said first and second transistors in proportion with the magnitude of said input signal and to vary the current flow through the collector-emitter path of said fourth transistor in inverse relationship to the magnitude of said input signal, the current flow in the collector-emitter path of said fourth transistor being equal to the difference between the constant current maintained by said source of biasing current and the biasing current flow through the parallel collectoremitter paths of said first and second transistors.
Claim 2
Dependent Claim
263 words
A dynamically biased amplifier comprising first and second transistors, d.c. biasing means connected to the base and emitter electrodes of each of said first and second transistors to bias said first and second transistors for operation as a differential amplifier, an input signal to be differentially amplified connected to the base electrode of said first transistor, a third transistor, a source of biasing current for maintaining a constant current therethrough, means connecting the collectoremitter paths of said first and second transistors in parallel, means serially connecting the parallel combination of the collector-emitter paths of said first and second transistors, the collector-emitter path of said third transistor, and said source of constant biasing current, a fourth transistor having its collector-emitter path connected across said source of biasing current to provide an alternate current path for a portion of the constant current maintained by said source of biasing current and means connecting said input signal to the base electrode of said third transistor and to the base electrode of said fourth transistor to vary the biasing current flow through the parallel collector-emitter paths of said first and second transistors in proportion with the magnitude of said input signal and to vary the current flow through the collector-emitter path of said fourth transistor in inverse relationship to the magnitude of said input signal, the current flow in the collector-emitter path of said fourth transistor being equal to the difference between the constant current maintained by said source of biasing current and the biasing current flow through the parallel collectoremitter paths of said first and second transistors.
Claim 3
Dependent Claim
66 words
A dynamically biased amplifier in accordance with claim 1 wherein said means connecting said input signal to the base electrode of said third transistor and to the base electrode of said fourth transistor includes a full wave rectifier having its positive output terminal connected to the base electrode of said third transistor and its negative output terminal connected to the base electrode of said fourth transistor.
Claim 4
Dependent Claim
187 words
A current folder and coder circuit comprising an unbalanced differential amplifier, a weighting and coding network connected to a comparator and logic circuit to control the reference signal from said weighting and coding network in accordance with the signal at the input of said comparator, a differential switch, a dynamic bias control network, a bias circuit, a source of biasing potential, means serially connecting said source of biasing potential, said weighting and coding network, said differential switch, said unbalanced differential amplifier, said dynaMic bias control network, and said bias circuit, a source of input signal, driving circuit means connected to said source of input signal and said differential switch to drive said differential switch in accordance with the polarity and frequency of said input signal, means connecting said unbalanced differential amplifier to said input signal source, and means connecting said dynamic bias control network to said input signal source to vary the current through the main coding path comprising said weighting and coding network, said differential switch, and said unbalanced differential amplifier in accordance with the instantaneous magnitude of the input signal from said input signal source.
Claim 5
Dependent Claim
187 words
A current folder and coder circuit comprising an unbalanced differential amplifier, a weighting and coding network connected to a comparator and logic circuit to control the reference signal from said weighting and coding network in accordance with the signal at the input of said comparator, a differential switch, a dynamic bias control network, a bias circuit, a source of biasing potential, means serially connecting said source of biasing potential, said weighting and coding network, said differential switch, said unbalanced differential amplifier, said dynaMic bias control network, and said bias circuit, a source of input signal, driving circuit means connected to said source of input signal and said differential switch to drive said differential switch in accordance with the polarity and frequency of said input signal, means connecting said unbalanced differential amplifier to said input signal source, and means connecting said dynamic bias control network to said input signal source to vary the current through the main coding path comprising said weighting and coding network, said differential switch, and said unbalanced differential amplifier in accordance with the instantaneous magnitude of the input signal from said input signal source.
Claim 6
Dependent Claim
56 words
A current folder and coder circuit comprising an unbalanced differential amplifier in accordance with claim 3 wherein a longitudinal compensation circuit is connected between said source of biasing potential and said weighting and coding network to compensate for the large voltage swings across said weighting and coding network in response to a large magnitude input signal.
Claim 7
Dependent Claim
135 words
A current folder and coder circuit comprising an unbalanced amplifier in accordance with claim 3 wherein said unbalanced differential amplifier comprises first and second transistors biased for operation as a differential amplifier, means connecting the source of input signal to the base electrode of said first transistor, means interconnecting the emitter electrodes of said first and second transistors, means including said differential switch and said weighting and coding network connect the collector electrodes of said first and second transistor in parallel in a main coding path to said source of bias potential, and said dynamic bias control circuit comprises at least a third transistor having its base electrode connected to said source of input signal and its collector-emitter path serially connected between the emitter electrodes of said first and second transistors and said bias circuit.
Claim 8
Dependent Claim
108 words
A current folder and coder circuit comprising an unbalanced differential amplifier in accordance with claim 5 wherein said dynamic biasing circuit includes a fourth transistor, means connecting the collector-emitter path of said fourth transistor from said source of biasing potential to said bias circuit, said bias circuit maintains a constant bias current, and means connecting the base electrode of said fourth transistor to said source of input signal to vary the current flow through the collector-emitter path of said fourth transistor in inverse relationship to the magnitude of the input signal from said input signal source and the current flow through the collector-emitter path of said third transistor.
Claim 9
Dependent Claim
145 words
A coder circuit comprising an unbalanced differential amplifier, a weighting and coding network connected to a comparator and logic circuit to control the reference signal from said weighting and coding network in accordance with the signal at the input of said comparator, a dynamic bias control network, a bias circuit, a source of bias potential, means serially connecting said source of biasing potential, said weighting and coding network, said unbalanced differential amplifier, said dynamic bias control network, and said bias circuit, a source of input signal, means connecting said unbalanced differential amplifier to said input signal source, and means connecting said dynamic bias control network to said input signal source to vary the current through the main coding path comprising said weighting and coding network, and said unbalanced differential amplifier in accordance with the instantaneous magnitude of the input signal from said input signal source.
Claim 10
Dependent Claim
145 words
A coder circuit comprising an unbalanced differential amplifier, a weighting and coding network connected to a comparator and logic circuit to control the reference signal from said weighting and coding network in accordance with the signal at the input of said comparator, a dynamic bias control network, a bias circuit, a source of bias potential, means serially connecting said source of biasing potential, said weighting and coding network, said unbalanced differential amplifier, said dynamic bias control network, and said bias circuit, a source of input signal, means connecting said unbalanced differential amplifier to said input signal source, and means connecting said dynamic bias control network to said input signal source to vary the current through the main coding path comprising said weighting and coding network, and said unbalanced differential amplifier in accordance with the instantaneous magnitude of the input signal from said input signal source.
References Cited (Backward Citations)
US3497824A
Cited
US3521179A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-04 | 1978-05-06 | 1978-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-04 | 1982-05-06 | 1982-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-04 | 1986-05-06 | 1986-11-05 | $7700.00 | Window Closed / Lapsed |