Dc restoration amplifier with automatic zero offset adjustment

Claim 2

A DC restoration amplifier for first signals having a first frequency range and DC offset signals having a sEcond frequency range lower than said first frequency range including in combination; first filter means having a filter response characteristic for coupling therethrough at least the range of frequencies of the first signals and offset signals coupled thereto, second filter means for coupling therethrough the range of frequencies of the DC offset signals coupled thereto, summing means coupled to said first and second filter means for subtracting said DC offset signals coupled thereto from said second filter means from said first signals and DC offset signals coupled thereto from said first filter means and develop resultant signals proportional to said first frequency range signals, and DC restoration means coupled to said summing means and responsive to said resultant signals to develop second signals corresponding to said first signals and having a DC reference bias of one-half the peak-to-peak amplitude of said second signals.

Claim 3

The DC restoration amplifier of claim 1 wherein said DC restoration means includes, circuit means for receiving said resultant signals and developing amplified resultant signals, peak-to-peak amplitude detector means coupled to said circuit means and operative to develop a bias signal equal to one-half the peak-to-peak amplitude of said amplified resultant signals, and DC level shifting means having a first input for receiving said amplified resultant signals and a second input for receiving said bias signal, said DC level shifting means being operative in response to said signals to develop said second signals.

Claim 4

The DC restoration amplifier of claim 2 wherein said DC level shifting means includes differential amplifier means having a first input for receiving said amplified resultant signals and a second input for receiving said bias signal.

Claim 5

The DC restoration amplifier of claim 3 wherein said summing means includes differential amplifier means having a first input coupled to said first filter means and a second input coupled to said second filter means.

Claim 6

The DC restoration amplifier of claim 4 wherein said first and second filter means are active filters having substantially unity gain.

Claim 7

The DC restoration amplifier of claim 5 wherein said peak-to-peak amplitude detector means includes first capacitance means having a first terminal for receiving said amplified resultant signals and a second terminal, first diode means having a first terminal coupled to said first capacitance means second terminal and a second terminal coupled to a source of potential, second diode means having a first terminal coupled to said first capacitance means second terminal and a second terminal, and second capacitance means having a first terminal coupled to said second diode means second terminal and a second terminal coupled to said source of potential, said differential amplifier means first input being coupled to said first capacitance means second terminal and said differential amplifier means second input being coupled to said second capacitance means first terminal.

Claim 8

The DC restoration amplifier of claim 6 wherein said circuit means includes, differential amplifier means having one input coupled to said summing means for receiving said resultant signals therefrom and a second input, bias means for providing a bias of one-half said source of potential coupled to said second input, said differential amplifier means being operative to develop said amplified resultant signals, said amplified resultant signals having a DC reference bias voltage of one-half said source of potential.

Claim 9

A DC restoration amplifier for restoring a DC reference bias to signals coupled thereto and wherein said amplifier operates from a source of potential, said amplifier including in combination, circuit means for receiving said signals and developing amplified signals, peak-to-peak amplitude detector means coupled to said circuit means and operative to develop a DC reference bias signal equal to one-half the peak-to-peak ampliTude of said amplified signals, and DC level shifting means having a first input for receiving said amplified signals and a second input for receiving said DC reference bias signals, said DC level shifting means being operative in response thereto to develop a second signal corresponding to said input signals and having a DC reference bias of one-half the peak-to-peak amplitude of said amplified signals.

Claim 10

A DC restoration amplifier for restoring a DC reference bias to signals coupled thereto and wherein said amplifier operates from a source of potential, said amplifier including in combination, circuit means for receiving said signals and developing amplified signals, peak-to-peak amplitude detector means coupled to said circuit means and operative to develop a DC reference bias signal equal to one-half the peak-to-peak ampliTude of said amplified signals, and DC level shifting means having a first input for receiving said amplified signals and a second input for receiving said DC reference bias signals, said DC level shifting means being operative in response thereto to develop a second signal corresponding to said input signals and having a DC reference bias of one-half the peak-to-peak amplitude of said amplified signals.

Claim 11

The DC restoration amplifier of claim 8 wherein said DC level shifting means includes differential amplifier means having a first input for receiving said amplified signals and a second input for receiving said bias signal.

Claim 12

The DC restoration amplifier of claim 9 wherein said circuit means includes differential amplifier means having one input for receiving said input signals and a second input, bias means for providing a bias of one-half said source of potential coupled to said second input, said differential amplifier means being operative to develop said amplified signals, said amplified signals having the same characteristics as said input signals and a reference bias voltage of one-half said source of potential.

Claim 13

The DC restoration amplifier of claim 10 wherein said peak-to-peak amplitude detector means includes first capacitance means having a first terminal for receiving said amplified signals and a second terminal, first diode means having a first terminal coupled to said first capacitance means second terminal and the second terminal coupled to a source of potential, second diode means having a first terminal coupled to said first capacitance means second terminal and a second terminal, and second capacitance means having a first terminal coupled to said second diode means second terminal and a second terminal coupled to said source of potential, said differential amplifier means first input being coupled to said first capacitance means second terminal, and said differential amplifier means second input being coupled to said second capacitance means first terminal.

Claim 14

An automatic zero offset adjustment circuit having input signals, including first frequency range signals and DC offset signals, coupled thereto, including in combination; first filter means having the input signals coupled thereto and a filter response characteristic for coupling therethrough at least the range of frequencies of the first frequency signals and DC offset signals, second filter means having the input signals coupled thereto and a frequency response characteristic for coupling therethrough the range of frequencies of the DC offset signals, summing means, including differential amplifier means, coupled to said first ans second filter means for subtracting said DC offset signals coupled thereto from said second filter means from said first frequency signals and DC offset signals coupled thereto from said first filter means to develop resultant signals proportional only to said first frequency signals, and connecting means for coupling between said first and second filter means to provide substantially equal response times of said first and second filter means in response to large amplitude DC offset signals.

Claim 15

An automatic zero offset adjustment circuit having input signals, including first frequency range signals and DC offset signals, coupled thereto, including in combination; first filter means having the input signals coupled thereto and a filter response characteristic for coupling therethrough at least the range of frequencies of the first frequency signals and DC offset signals, second filter means having the input signals coupled thereto and a frequency response characteristic for coupling therethrough the range of frequencies of the DC offset signals, summing means, including differential amplifier means, coupled to said first ans second filter means for subtracting said DC offset signals coupled thereto from said second filter means from said first frequency signals and DC offset signals coupled thereto from said first filter means to develop resultant signals proportional only to said first frequency signals, and connecting means for coupling between said first and second filter means to provide substantially equal response times of said first and second filter means in response to large amplitude DC offset signals.

Claim 16

The circuit of claim 12 wherein said first and second filter means are active filters having substantially unity gain and wherein said connecting means includes a pair of oppositely connected parallel diodes.

Claim 17

The circuit of claim 13 wherein said first filter means has a filter response characteristic for passing signals from DC to 180 Hz, and said second filter means has a filter response characteristic for passing signals from DC to 3 Hz.