US3846698A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Overcurrent events monitoring system
Assignee: ABB Inc USA
•
Filing: 1973-09-25
•
Granted: 1974-11-05
•
Expires: 1993-09-25
Abstract
Abstract An overcurrent events monitoring system includes a monitor unit having digital logic and constant linear timing circuits to count and store both the total of overcurrent events occurring in an electrical circuit under test and the number of overcurrent events which are sustained. A readout and tester unit is detachably connected to the monitor for interrogating and testing a monitor unit. A numerical display visually indicates the events stored in the monitor unit binary counters which are resettable after the counter readouts are provided.
Inventors
- 👤 D Lawton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 01:47
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/165; G01R19/16566; G01R19/16571; H; H01; H01F; H01F27/00; H01F27/40; H01F27/402
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
462 words
In an overcurrent events monitoring system, a monitor unit for digitally distinguishing and counting momentary and sustained occurrences of excessive current magnitudes in a circuit under test, said monitor unit comprising: a logical threshold detector including an input and an output, said input being responsive to each of said occurrences of excessive current magnitudes, and said output developing first logic signals of first and second states having transitions therebetween in one and opposite directions upon each of said occurrences and at the end of said occurrences, respectively; a pulse stretcher including a logic gate circuit including an input and an output, said output developing second logic signals of first and second states having transitions therebetween in one and opposite directions, said input being responsive to said one direction of transistion of said first logic signals so as to develop a normal gate circuit transition in one direction to effect a transition in said second logic signals in said one direction, and said pulse stretcher further including a time delay circuit means connected between said input and said output of the gate circuit to effect a linearly extended transition in an opposite direction in said second logic signals in response to said opposite direction of transition in said first logic signals; a first binary counter responsive to said one direction of transition in said second logic signals so as to accumulate the total of occurrences of excessive current magnitudes occurring at intervals substantially equal to or longer than the linearly extended transition in said second logic signals; a pulse interval recognition circuit including a logic gate circuit including an input and an output, and a time delay circuit means connected between said input and said output and externally of said gate circuit, said input being responsive to said second logic signals, said output developing third logic signals of first and second states having transitions in one and opposite directions therebetween, said third logic signals having a transition in said one direction in response to a normal gate circuit transition in said one direction between said first and second states in response to the opposite direction of transition in said second logic signals, said third logic signal having a linearly extended transition in an opposite direction between said first and second states, said last named extended transition in said third logic signals being established by said time delay circuit means so as to be longer than the extended transition in said second logic signal, and a second binary counter means responsive to said opposite direction of transition in said third logic signals so as to accumulate the number of sustained occurrences of excessive current magnitudes occurring during an interval substantially equal to or longer than said linearly extended transition in said third logic signals.
Claim 2
Dependent Claim
462 words
In an overcurrent events monitoring system, a monitor unit for digitally distinguishing and counting momentary and sustained occurrences of excessive current magnitudes in a circuit under test, said monitor unit comprising: a logical threshold detector including an input and an output, said input being responsive to each of said occurrences of excessive current magnitudes, and said output developing first logic signals of first and second states having transitions therebetween in one and opposite directions upon each of said occurrences and at the end of said occurrences, respectively; a pulse stretcher including a logic gate circuit including an input and an output, said output developing second logic signals of first and second states having transitions therebetween in one and opposite directions, said input being responsive to said one direction of transistion of said first logic signals so as to develop a normal gate circuit transition in one direction to effect a transition in said second logic signals in said one direction, and said pulse stretcher further including a time delay circuit means connected between said input and said output of the gate circuit to effect a linearly extended transition in an opposite direction in said second logic signals in response to said opposite direction of transition in said first logic signals; a first binary counter responsive to said one direction of transition in said second logic signals so as to accumulate the total of occurrences of excessive current magnitudes occurring at intervals substantially equal to or longer than the linearly extended transition in said second logic signals; a pulse interval recognition circuit including a logic gate circuit including an input and an output, and a time delay circuit means connected between said input and said output and externally of said gate circuit, said input being responsive to said second logic signals, said output developing third logic signals of first and second states having transitions in one and opposite directions therebetween, said third logic signals having a transition in said one direction in response to a normal gate circuit transition in said one direction between said first and second states in response to the opposite direction of transition in said second logic signals, said third logic signal having a linearly extended transition in an opposite direction between said first and second states, said last named extended transition in said third logic signals being established by said time delay circuit means so as to be longer than the extended transition in said second logic signal, and a second binary counter means responsive to said opposite direction of transition in said third logic signals so as to accumulate the number of sustained occurrences of excessive current magnitudes occurring during an interval substantially equal to or longer than said linearly extended transition in said third logic signals.
Claim 3
Dependent Claim
109 words
The overcurrent events monitoring system as claimed in claim 1, wherein said pulse stretcher of said monitor unit includes said time delay circuit means having a capacitor connected between said input and said output of said logic gate circuit, and further has a resistor connected in series with said input of said logic gate circuit to establish a predetermined charging time for said capacitor and thereby control said linearly extended transition in said opposite direction in said second logic signals, said time delay circuit means further including a diode connected across said resistor to effect the normal gate circuit transition in said one direction in said second logic signals.
Claim 4
Dependent Claim
125 words
The overcurrent events monitoring system as claimed in claim 2, wherein said pulse interval recognition circuit of said monitor unit includes said time delay circuit means having a capacitor connected between said input and said output of said logic gate circuit, and further has a resistor connected in series with said input of said logic gate circuit to establish a predetermined charging time for said capacitor which is longer than the charging time of said capacitor of said pulse stretcher and thereby control the linearly extended transition in said opposite direction in said third logic signals, said time delay circuit means further including a diode connected across said resistor to effect the normal gate circuit transistor in said one direction in said third logic signals.
Claim 5
Dependent Claim
75 words
The overcurrent events monitoring system of claim 1, wherein said excessive current magnitudes in the circuit under test occur in a current having a frequency of substantially sixty hertz, and wherein said linearly extended transition of said second logic signals is slightly longer than between one to two cycles of the current frequency, and further wherein said linearly extended transition of said third logic signals is slightly longer than ten cycles of the current frequency.
Claim 6
Dependent Claim
39 words
The overcurrent events monitoring system of claim 3, wherein each of said logic gate circuits of said pulse stretcher and said pulse interval recognition circuit includes a separate two input NAND gate having said two inputs thereof connected together.
Claim 7
Dependent Claim
52 words
The overcurrent events monitoring system of claim 1, including a plurality of pairs of input terminals, predetermined pairs of said pairs of input terminals each including one input terminal being connected to a direct current voltage source and the other input terminal being connected with said input of said logical threshold detector.
Claim 8
Dependent Claim
51 words
The overcurrent events monitoring system of claim 6, including a magnetically actuated switch inductively coupled to said circuit under test so as to effect a switch closure in response to said occurrence of excessive current magnitude, said magnetically actuated switch being connected across one of said predetermined pairs of input terminals.
Claim 9
Dependent Claim
100 words
The overcurrent events monitoring system of claim 1, including connector means having a terminal connected to outputs of said first and second binary counters, said system further including a readout and tester unit, said readout and tester unit having connector means detachably mating with said connector of said monitor unit, said readout and tester unit further having a decoding and numerical display section having a binary coded decimal converter and a numerical readout light means, said converter being connected between said connector and said readout light means for displaying the numerical count contained in said first and second binary counters.
Claim 10
Dependent Claim
169 words
The overcurrent events monitoring system of claim 8, wherein said readout and tester unit has a first, a second and a third set of logic gate circuits having gating and enabling inputs, said first and second sets of logic gate circuits having said gating inputs connected to said connector so as to be connected to said first and to said second binary counters, respectively, said gating and enabling inputs of said third set of logic gate circuits being connected to the outputs of said first and second sets of said logic gate circuits, gate enabling circuit means including a selector switch connected to said enabling inputs of said first and second sets of logic circuits so that the position of said selector switch provides outputs from one or the other of said first and second sets of logic gate circuits that is effective to develop corresponding outputs from said third set of logic circuits, and the outputs of said third set being connected to said binary to binary-coded-decimal converter.
Claim 11
Dependent Claim
77 words
The overcurrent events monitoring system as claimed in claim 9, wherein said monitor unit includes a battery power supply; said readout and tester unit includes a battery power supply and a solid state voltage responsive circuit incLuding an indicator means connected through said connectors of said monitor and said readout and tester unit and across said battery power supply of said monitor unit to provide an indication of the condition of the monitor unit battery power supply.
References Cited (Backward Citations)
US3775675A
Cited
US3789293A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-04 | 1978-05-06 | 1978-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-04 | 1982-05-06 | 1982-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-04 | 1986-05-06 | 1986-11-05 | $7700.00 | Window Closed / Lapsed |