US3846644A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Intermittently driving circuit for a load such as a buzzer or a bell
Assignee: Tokai Rika Co Ltd
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Filing: 1973-07-02
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Granted: 1974-11-05
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Expires: 1993-07-02
Abstract
Abstract An intermittently driving circuit for a load such as a buzzer or a bell which by itself interrupts a current flowing therethrough. An SCR is connected in series with the load and a charge-anddischarge circuit including a capacitor is connected between a gate and a cathode of the SCR. The SCR is turned on after a charging period of the charge-and-discharge circuit for driving the load, while it is turned off after a discharging period of the charge-and-discharge circuit by the current interrupting operation of the load to stop driving of the load.
Inventors
- 👤 S Takagi
- 👤 I Kawashima
- 👤 K Takagi
- 👤 S Hibino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:04
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/35; H03K3/352; G; G08; G08B; G08B3/00; G08B3/10; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/10; H02M3/125; H02M3/135
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
347 words
An intermittent driving circuit, comprising in combination: an SCR having a gate; a capacitor and coupling means connecting said capacitor to said gate; a voltage source, a switch and a first resistor; means defining a first loop connecting in series said voltage source, switch, first resistor and capacitor and responsive to closure of said switch for charging said capacitor to a level sufficient to fire said SCR; means defining a second loop connecting in series said SCR, said voltage source and said switch for supplying sufficient SCR anode current to maintain SCR conduction when said second loop is closed; a self interrupting load and means connecting same in series in said first and second loops for interrupting current flow through said second loop after energization by SCR current flow in said second loop; means defining a third loop omitting said self interrupting load and connecting in series said SCR, said capacitor and at least said first resistor for discharging said capacitor through at least said first resistor to the anode of said SCR over a first time period independent of SCR conduction through said self interrupting load and for thereafter turning off said SCR upon simultaneous occurrence of capacitor discharge current less than the anode holding current of said SCR and a current interruption by said self interrupting load; a transistor having collector and emitter electrodes connected between said capacitor and the anode of said SCR and a base bias circuit for said transistor connected across said series SCR and self interrupting load, said transistor having a base electrode connected intermediate the ends of said bias circuit, the collector and emitter terminals of said transistor being coupled in series with a second resistor across said first resistor, said base bias circuit includiNg a resistive voltage divider and a further capacitor in series, whereby upon closure of said switch said transistor rapidly charges said first mentioned capacitor so as to substantially immediately cause said SCR to drive said self interrupting load but wherein said transistor is nonconductive for subsequent energizations of said self interrupting load by said SCR.
Claim 2
Dependent Claim
347 words
An intermittent driving circuit, comprising in combination: an SCR having a gate; a capacitor and coupling means connecting said capacitor to said gate; a voltage source, a switch and a first resistor; means defining a first loop connecting in series said voltage source, switch, first resistor and capacitor and responsive to closure of said switch for charging said capacitor to a level sufficient to fire said SCR; means defining a second loop connecting in series said SCR, said voltage source and said switch for supplying sufficient SCR anode current to maintain SCR conduction when said second loop is closed; a self interrupting load and means connecting same in series in said first and second loops for interrupting current flow through said second loop after energization by SCR current flow in said second loop; means defining a third loop omitting said self interrupting load and connecting in series said SCR, said capacitor and at least said first resistor for discharging said capacitor through at least said first resistor to the anode of said SCR over a first time period independent of SCR conduction through said self interrupting load and for thereafter turning off said SCR upon simultaneous occurrence of capacitor discharge current less than the anode holding current of said SCR and a current interruption by said self interrupting load; a transistor having collector and emitter electrodes connected between said capacitor and the anode of said SCR and a base bias circuit for said transistor connected across said series SCR and self interrupting load, said transistor having a base electrode connected intermediate the ends of said bias circuit, the collector and emitter terminals of said transistor being coupled in series with a second resistor across said first resistor, said base bias circuit includiNg a resistive voltage divider and a further capacitor in series, whereby upon closure of said switch said transistor rapidly charges said first mentioned capacitor so as to substantially immediately cause said SCR to drive said self interrupting load but wherein said transistor is nonconductive for subsequent energizations of said self interrupting load by said SCR.
Claim 3
Dependent Claim
31 words
A circuit as claimed in claim 1, in which said coupling means comprises a further resistor and including an additional resistor connected in series with said further resistor across said capacitor.
Claim 4
Dependent Claim
44 words
A circuit as claimed in claim 1, in which said voltage divider comprises third and fourth resistors in series, said third resistor being connected between said second resistor and said transistor base, said second resistor being substantially smaller in value than said first resistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-04 | 1978-05-06 | 1978-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-04 | 1982-05-06 | 1982-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-04 | 1986-05-06 | 1986-11-05 | $7700.00 | Window Closed / Lapsed |