Abstract 1. A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING THE STEPS OF (A) PROVIDING A SEMICONDUCTOR SUBSTRATE COMPRISING AT LEAST ONE NPN TRANSISTOR AND AN INSULATING LAYER HAVING APERTURES FOR EXPOSING PART OF THE ENTIRE REGION AND BASED REGION OF SAID TRANSISTOR, RESPECTIVELY, SAID INSULATING LAYER COVERING SAID TRANSISTOR, (B) FORMING A METAL LAYER ON SAID EXPOSED EMITTER REGION AND ON SAID EXPOSED REGION, RESPECTIVELY, AND ON AT LEAST A PORTION OF SAID INSULATING LAYER ADJACENT SAID EXPOSED REGIONS, AND METAL LAYERS BEING CAPABLE OF BEING ETCHED ELECTROLYTICALLY, (C) IMMERSING SAID SUBSTRATE AND AN ELECTRODE APART FROM EACH OTHER IN A SOLUTION CAPABLE OF ELECTROLYTICALLY ETCHING SAID METAL LAYER, AND APPLYING A PREDETERMINED MAGNITUDE OF VOLTAGE BETWEEN THE COLLECTOR OF SAID TRANSISTOR OR SAID ELECTRODE FOR A PREDETERMINED PERIOD OF TIME IN SUCH A DIRECTION AS TO MAINTAIN SAID COLLECTOR POSITIVE WITH RESPECT TO SAID ELECTRODE, THEREBY ACCOMPLISHING AN ELECTROLYTIC ETCHING PROCESS, SAID VOLTAGE BEING RELATIVELY HIGH BUT SUFFICIENTLY LOW TO APPLY TO THE PN JUNCTION BETWEEN SAID COLLECTOR AND SAID BASE A VOLTAGE NOT EXCEEDING THE RATED REVERSE BREAKDOWN VOLTAGE OF SAID PN JUNCTION, SAID PERIOD OF TIME BEING SO LONG THAT SAID METAL LAYERS ARE ELECTROLYTICALLY ETCHED BY A CURRENT WHICH FLOWS WHEN SAID PN JUNCTION IS RUPTURED BY SAID APPLIED VOLTAGE; WHEREBY THE METAL LAYERS ON THE EMITTER AND THE REGIONS ARE RETAINED OR REMOVED DEPENDING ON WHETHER SAID PN JUNCTION IS CAPABLE OF ENDURING SAID APPLIED VOLTAGE. (D) AND FORMING ON SAID INSULATING LAYER WIRING CONDUCTOR LAYERS HAVING A PORTION EXTENDING TO A POINT WHERE SAID WIRING CONDUCTOR LAYERS ARE CAPABLE OF CONNECTING WITH THE RETAINED METAL LAYERS RESPECTIVELY ON THE BASE AND EMITTER REGIONS WHEREBY THE CONDUCTOR LAYERS ARE CONNECTED ONLY WITH THE BASE AND EMITTER REGION OF THE TRANSISTOR WHOSE PN JUNCTION BETWEEN SAID COLLECTOR AND BASE REGIONS IS CAPABLE OF ENDURING SAID RATED REVERSE BREAKDOWN VOLTAGE.
A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING THE STEPS OF (A) PROVIDING A SEMICONDUCTOR SUBSTRATE COMPRISING AT LEAST ONE NPN TRANSISTOR AND AN INSULATING LAYER HAVING APERTURES FOR EXPOSING PART OF THE ENTIRE REGION AND BASED REGION OF SAID TRANSISTOR, RESPECTIVELY, SAID INSULATING LAYER COVERING SAID TRANSISTOR, (B) FORMING A METAL LAYER ON SAID EXPOSED EMITTER REGION AND ON SAID EXPOSED REGION, RESPECTIVELY, AND ON AT LEAST A PORTION OF SAID INSULATING LAYER ADJACENT SAID EXPOSED REGIONS, AND METAL LAYERS BEING CAPABLE OF BEING ETCHED ELECTROLYTICALLY, (C) IMMERSING SAID SUBSTRATE AND AN ELECTRODE APART FROM EACH OTHER IN A SOLUTION CAPABLE OF ELECTROLYTICALLY ETCHING SAID METAL LAYER, AND APPLYING A PREDETERMINED MAGNITUDE OF VOLTAGE BETWEEN THE COLLECTOR OF SAID TRANSISTOR OR SAID ELECTRODE FOR A PREDETERMINED PERIOD OF TIME IN SUCH A DIRECTION AS TO MAINTAIN SAID COLLECTOR POSITIVE WITH RESPECT TO SAID ELECTRODE, THEREBY ACCOMPLISHING AN ELECTROLYTIC ETCHING PROCESS, SAID VOLTAGE BEING RELATIVELY HIGH BUT SUFFICIENTLY LOW TO APPLY TO THE PN JUNCTION BETWEEN SAID COLLECTOR AND SAID BASE A VOLTAGE NOT EXCEEDING THE RATED REVERSE BREAKDOWN VOLTAGE OF SAID PN JUNCTION, SAID PERIOD OF TIME BEING SO LONG THAT SAID METAL LAYERS ARE ELECTROLYTICALLY ETCHED BY A CURRENT WHICH FLOWS WHEN SAID PN JUNCTION IS RUPTURED BY SAID APPLIED VOLTAGE; WHEREBY THE METAL LAYERS ON THE EMITTER AND THE REGIONS ARE RETAINED OR REMOVED DEPENDING ON WHETHER SAID PN JUNCTION IS CAPABLE OF ENDURING SAID APPLIED VOLTAGE.
Claim 2
Independent Claim
240 words
A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING THE STEPS OF (A) PROVIDING A SEMICONDUCTOR SUBSTRATE COMPRISING AT LEAST ONE NPN TRANSISTOR AND AN INSULATING LAYER HAVING APERTURES FOR EXPOSING PART OF THE ENTIRE REGION AND BASED REGION OF SAID TRANSISTOR, RESPECTIVELY, SAID INSULATING LAYER COVERING SAID TRANSISTOR, (B) FORMING A METAL LAYER ON SAID EXPOSED EMITTER REGION AND ON SAID EXPOSED REGION, RESPECTIVELY, AND ON AT LEAST A PORTION OF SAID INSULATING LAYER ADJACENT SAID EXPOSED REGIONS, AND METAL LAYERS BEING CAPABLE OF BEING ETCHED ELECTROLYTICALLY, (C) IMMERSING SAID SUBSTRATE AND AN ELECTRODE APART FROM EACH OTHER IN A SOLUTION CAPABLE OF ELECTROLYTICALLY ETCHING SAID METAL LAYER, AND APPLYING A PREDETERMINED MAGNITUDE OF VOLTAGE BETWEEN THE COLLECTOR OF SAID TRANSISTOR OR SAID ELECTRODE FOR A PREDETERMINED PERIOD OF TIME IN SUCH A DIRECTION AS TO MAINTAIN SAID COLLECTOR POSITIVE WITH RESPECT TO SAID ELECTRODE, THEREBY ACCOMPLISHING AN ELECTROLYTIC ETCHING PROCESS, SAID VOLTAGE BEING RELATIVELY HIGH BUT SUFFICIENTLY LOW TO APPLY TO THE PN JUNCTION BETWEEN SAID COLLECTOR AND SAID BASE A VOLTAGE NOT EXCEEDING THE RATED REVERSE BREAKDOWN VOLTAGE OF SAID PN JUNCTION, SAID PERIOD OF TIME BEING SO LONG THAT SAID METAL LAYERS ARE ELECTROLYTICALLY ETCHED BY A CURRENT WHICH FLOWS WHEN SAID PN JUNCTION IS RUPTURED BY SAID APPLIED VOLTAGE; WHEREBY THE METAL LAYERS ON THE EMITTER AND THE REGIONS ARE RETAINED OR REMOVED DEPENDING ON WHETHER SAID PN JUNCTION IS CAPABLE OF ENDURING SAID APPLIED VOLTAGE.