Bistable electronic circuit

Claim 2

A bistable electronic circuit of the flip-flop latch type comprising, in combination: a data input terminal for supplying a data signal, a first clock input point for supplying a clock signal, a second clock input point for supplying an inverted clock signal, at least one data output terminal for delivering data in inverted logical sense, first, second and third circuit elements for performing the logical AND function, each of said circuit elements having at least two input terminals and an output terminal; a fourth circuit element for performing the logical NOR function, said fourth circuit element having three input terminals and one output terminal, a fifth circuit element for performing a logical inversion, said fifth circuit element having at least one input terminal and one output terminal, the two input terminals of said first circuit element being connected respectively to said data input terminal and to said first clock input point, the two input terminals of said second circuit element being connected respectively to the second clock input point and to the output terminal of said fifth circuit element, the two input terminals of said third circuit element being connected respectively to said data input terminal and to the output terminal of said fifth circuit element, the output terminals of said first, second and third circuit elements being connected respectively to one of the input terminals of said fourth circuit element, and the output terminal of said fourth circuit element being connected to said data output terminal and being directly connected to a first input terminal of said fifth circuit element for controlling the state of said fifth circuit element in substantially direct response to operation of said fourth circuit element independently of the data signal.

Claim 3

The bistable electronic circuit of claim 1 wherein said fifth circuit element includes additional apparatus for performing the logical NOR function and is provided with a second input terminal, and wherein said bistable electronic circuit further comprises a presetting input terminal connected to said second input terminal of said fifth element.

Claim 4

The bistable electronic circuit of claim 2 wherein said electronic circuit is fabricated according to integrated circuit technology, said fabrication causing an inverting operation to occupy a time interval less than Delta and a non-inverting operation to occupy a time interval negligible compared to Delta , a signal on said data output terminal responding to said data signal within a time interval 2 Delta when said clock signal is applied to said first clock input point.

Claim 5

The bistable electronic circuit of claim 1 wherein said fifth element includes additional apparatus for performing the logical NAND function and is provided with a second input terminal and wherein said bistable electronic circuit further comprises a presetting input terminal connected to said second input terminal of said fifth element.

Claim 6

A bistable electronic circuit of the flip-flop latch type comprising, in combination: a data input terminal for supplying a data signal, a clock input terminal for supplying a clock signal, at least one data output terminal for delivering inverted data in inverted logical sense, first, second and third circuit elements for performing the logical AND function, each of said circuit elements having at least two input terminals and one output terminal, a fourth circuit element for performing the logical NOR functioN and having at least three input terminals and one output terminal, a fifth circuit element for performing a logical inversion and having at least one input terminal and one output terminal, a sixth circuit element for performing the logical inversion function and having one input terminal and one output terminal, the input terminal of said sixth circuit element being connected to said clock input terminal, the two input terminals of said first circuit element being connected respectively to said data input terminal and to said clock input terminal, the two input terminals of said second circuit element being connected respectively to the output terminal of said sixth circuit element and to the output terminal of said fifth circuit element, the two input terminals of said third circuit element being connected respectively to said data input terminal and to the output terminal of said fifth circuit element, the output terminals of said first, second and third circuit elements being connected respectively to one of the input terminals of said fourth circuit element and the output terminal of said fourth circuit element being connected to said data output terminal and being directly connected to a first input terminal of said fifth circuit element for controlling the state of said fifth circuit element in substantially direct response to operation of said fourth circuit element independently of the data signal.

Claim 7

A bistable electronic circuit of the flip-flop latch type comprising, in combination: a data input terminal for supplying a data signal, a clock input terminal for supplying a clock signal, at least one data output terminal for delivering inverted data in inverted logical sense, first, second and third circuit elements for performing the logical AND function, each of said circuit elements having at least two input terminals and one output terminal, a fourth circuit element for performing the logical NOR functioN and having at least three input terminals and one output terminal, a fifth circuit element for performing a logical inversion and having at least one input terminal and one output terminal, a sixth circuit element for performing the logical inversion function and having one input terminal and one output terminal, the input terminal of said sixth circuit element being connected to said clock input terminal, the two input terminals of said first circuit element being connected respectively to said data input terminal and to said clock input terminal, the two input terminals of said second circuit element being connected respectively to the output terminal of said sixth circuit element and to the output terminal of said fifth circuit element, the two input terminals of said third circuit element being connected respectively to said data input terminal and to the output terminal of said fifth circuit element, the output terminals of said first, second and third circuit elements being connected respectively to one of the input terminals of said fourth circuit element and the output terminal of said fourth circuit element being connected to said data output terminal and being directly connected to a first input terminal of said fifth circuit element for controlling the state of said fifth circuit element in substantially direct response to operation of said fourth circuit element independently of the data signal.

Claim 8

The bistable electronic circuit of claim 5, wherein said fifth circuit element includes additional apparatus for performing the logical NOR function and is provided with a second input terminal and wherein said bistable electronic circuit further comprises a presetting input terminal connected to said second input terminal of said fifth circuit element.

Claim 9

The bistable electronic circuit of claim 6, wherein said circuit is manufactured according to integrated circuit techniques, wherein said techniques cause an inverting operation to occupy a time interval less than Delta and a non-inverting operation to occupy a time interval negligible compared to Delta , said data signal resulting in said inverted data in a time interval less than 2 Delta when said clock signal is applied.

Claim 10

The bistable electronic circuit of claim 5 wherein said fifth circuit element includes additional apparatus for performing the logical NAND function and is provided with a second input terminal, and wherein said bistable electronic circuit further comprises a presetting input terminal connected to said second input terminal of said fifth circuit element.

Claim 11

A bistable logical configuration for receiving a clock signal and a data signal operative in one of two levels and for storing a representation of said data signal when said clock signal has a predetermined value, comprising: first, second and third AND gates, each of said AND gates receiving a pair of input signals at respective input terminals thereof and delivering an output signal representing the AND operation on the two signals received thereby at an output terminal thereof, a NOR gate receiving three input signals at respective input terminals thereof and delivering an output signal representing the NOR operation on the three signals received thereby at an output terminal thereof, an inverter receiving an input signal at an input terminal thereof and delivering an output signal representing the logical inversion of the signal received thereby, means coupling the output terminals of said first, second and third AND gates to respective input terminals of said NOR gate, means for directly connecting the output terminal of said NOR gate to the input terminal of said inverter for controlling the operation of said inverter in substantially direct response to operation of said NOR gate independently of said data signal, means for applying said clock signal to one input terminal of said first AND gate, means for applying a logical inversion of said clock signal to one input terminal of said second AND gate, means for applying said data signal to the other input terminal of said first AND gate and to the input terminal of said third AND gate, and means for applying the output signal of said inverter to the other input terminal of said second and third AND gates.

Claim 12

A bistable logical configuration for receiving a clock signal and a data signal operative in one of two levels and for storing a representation of said data signal when said clock signal has a predetermined value, comprising: first, second and third AND gates, each of said AND gates receiving a pair of input signals at respective input terminals thereof and delivering an output signal representing the AND operation on the two signals received thereby at an output terminal thereof, a NOR gate receiving three input signals at respective input terminals thereof and delivering an output signal representing the NOR operation on the three signals received thereby at an output terminal thereof, an inverter receiving an input signal at an input terminal thereof and delivering an output signal representing the logical inversion of the signal received thereby, means coupling the output terminals of said first, second and third AND gates to respective input terminals of said NOR gate, means for directly connecting the output terminal of said NOR gate to the input terminal of said inverter for controlling the operation of said inverter in substantially direct response to operation of said NOR gate independently of said data signal, means for applying said clock signal to one input terminal of said first AND gate, means for applying a logical inversion of said clock signal to one input terminal of said second AND gate, means for applying said data signal to the other input terminal of said first AND gate and to the input terminal of said third AND gate, and means for applying the output signal of said inverter to the other input terminal of said second and third AND gates.

Claim 13

A bistable logical configuration for receiving a clock signal operative in one of two levels and designated by the binary variable C and a data signal operative in one of two levels and designated by the binary variable D, wherein said logical configuration stores a representation of said data signal when said clock signal is at a predetermined level, comprising: first, second and third logical elements each receiving a pair of input signals and delivering an output signal representing the AND operation on the two signals received thereby, a fourth logical element for receiving three input signals and for delivering an output signal designated by the binary variable Q, a fifth logical element for performing a logic inversion, said fifth logical element having at least one input terminal and at least one output terminal for supplying a complementary output signal designated by the binary variable Q, means for applying said clock signal to said first logical element, means for applying said data signal to said first and second logical element, means for applying a logical inversion of said clock signal to said third logical element, means for applying said output signal of the fourth logical element to said second and third logical elements, means for applying said output signals of the first, second, and third logical element to said fourth logical element, and means for directly applying said output signal of said fourth logical element to the input terminal of said fifth circuit element independently of said data signal, wherein said fifth logical element comprises a logical configuration for delivering a complementary output signal which represents the C.D + Q.D + Q.C logical operation on the signals received thereby.

Claim 14

A bistable logical configuration for receiving a clock signal operative in one of two levels and designated by the binary variable C and a data signal operative in one of two levels and designated by the binary variable D, wherein said logical configuration stores a representation of said data signal when said clock signal is at a predetermined level, comprising: first, second and third logical elements each receiving a pair of input signals and delivering an output signal representing the AND operation on the two signals received thereby, a fourth logical element for receiving three input signals and for delivering an output signal designated by the binary variable Q, a fifth logical element for performing a logic inversion, said fifth logical element having at least one input terminal and at least one output terminal for supplying a complementary output signal designated by the binary variable Q, means for applying said clock signal to said first logical element, means for applying said data signal to said first and second logical element, means for applying a logical inversion of said clock signal to said third logical element, means for applying said output signal of the fourth logical element to said second and third logical elements, means for applying said output signals of the first, second, and third logical element to said fourth logical element, and means for directly applying said output signal of said fourth logical element to the input terminal of said fifth circuit element independently of said data signal, wherein said fifth logical element comprises a logical configuration for delivering a complementary output signal which represents the C.D + Q.D + Q.C logical operation on the signals received thereby.

Claim 15

The bistable logical configuration of claim 10 wherein said configuration is fabricated by integrated circuit technology, an inverting operation occupying a time interval less than Delta and a non-inverting operation occupying a time interval negligible compared to Delta , said Q and said Q responding to a data signal within a time 2 Delta when said clock signal is at said predetermined level.

Claim 16

A bistable logical configuration for receiving a clock signal and a data signal operative in one of two levels and for storing a representation of said data signal when said clock signal has a predetermined value, said logical configuration fabricated according to a technique wherein an inverting operation occupies a delay time less than Delta and a non-inverting operation occupies a delay time negligible compared to Delta , comprising: first, second and third AND gates, each of said AND gates receiving a pair of input signals at respective input terminals thereof and delivering an output signal representing the AND operation on the two signals received thereby at an output terminal thereof, a NOR gate receiving three input signals at respective input terminals thereof and delivering an output signal representing the NOR operation on the three signals received thereby at an output terminal thereof, an inverter receiving an input signal at an input terminal thereof and delivering an output signal representing the logical inversion of the signal received thereby, means coupling the output terminals of said first, second and third AND gates to respective input terminals of said NOR gate, means for directly connecting the output terminal of said NOR gate to the input terminal of said inverter for controlling the operation of said inverter in substantially direct response to operation of said NOR gate independently of the data signal, means for applying said clock signal to one input terminal of said first AND gate, means for applyinG a logical inversion of said clock signal to one input terminal of said second AND gate, means for applying said data signal to the other input terminal of said first AND gate and to the input terminal of said third AND gate, and means for applying the output signal of said inverter to the other input terminal of said second and third AND gates, said output signal of said inverter and an output signal of said NOR gate responding to said data signal within a delay time of 2 Delta when said clock signal has said predetermined value.

Claim 17

A bistable logical configuration for receiving a clock signal and a data signal operative in one of two levels and for storing a representation of said data signal when said clock signal has a predetermined value, said logical configuration fabricated according to a technique wherein an inverting operation occupies a delay time less than Delta and a non-inverting operation occupies a delay time negligible compared to Delta , comprising: first, second and third AND gates, each of said AND gates receiving a pair of input signals at respective input terminals thereof and delivering an output signal representing the AND operation on the two signals received thereby at an output terminal thereof, a NOR gate receiving three input signals at respective input terminals thereof and delivering an output signal representing the NOR operation on the three signals received thereby at an output terminal thereof, an inverter receiving an input signal at an input terminal thereof and delivering an output signal representing the logical inversion of the signal received thereby, means coupling the output terminals of said first, second and third AND gates to respective input terminals of said NOR gate, means for directly connecting the output terminal of said NOR gate to the input terminal of said inverter for controlling the operation of said inverter in substantially direct response to operation of said NOR gate independently of the data signal, means for applying said clock signal to one input terminal of said first AND gate, means for applyinG a logical inversion of said clock signal to one input terminal of said second AND gate, means for applying said data signal to the other input terminal of said first AND gate and to the input terminal of said third AND gate, and means for applying the output signal of said inverter to the other input terminal of said second and third AND gates, said output signal of said inverter and an output signal of said NOR gate responding to said data signal within a delay time of 2 Delta when said clock signal has said predetermined value.