Bidirectional line driver-receiver circuit

Claim 2

A data transmission line system for interconnecting a plurality of terminal devices through a two conductor line for communication, said system comprising: a plurality of transmitreceive elements, T-R1 through T-Rn, each element being coupled to a different one of said terminal devices for transmitting and receiving bilevel information between said one device and said line, said element having at least a pair of line terminals, each one of said line terminals being coupled to a different one of the conductors of said line, a data terminal TVD, for receiving a bilevel data input signal from said terminal device, a gate input terminal, TVG, for receiving a bilevel control switching signal from said device, and a receiver terminal, TVR, for passing a bilevel logic signal from said transmit-receive element to said device in response to information signals applied to said line terminals and each of said elements further including first and second amplifiers, said first amplifier having first and second inputs and at least one output, said second amplifier having an input and first and second outputs, said inputs respectively of said first amplifier being connected to said line terminals in common with said first and second outputs of said second amplifier, said output of said first amplifier being coupled to said receiver terminal, TVR, said data terminal, TVD, being coupled to said input of said second amplifier; a bias voltage source; means for connecting one of said conductors of said line to said source and the other of said conductors of said line to a reference potential; and, means for applying at least one bilevel logic switChing signal to said first and second amplifiers from each of said TVG input terminals from said devices to define a transmit-receive mode of operation for each of said elements and said system.

Claim 3

The system of claim 1 wherein said system transmit-receive mode is half-duplex for which the logic signal applied to said TVG terminal of one of said elements is set to a one level of said bilevel signal and the logic signal applied to the TVG terminal of the remaining elements is set to the other level of said bilevel signal.

Claim 4

A differential line driver-receiver device comprising: a first differential amplifier including a pair of input circuits for receiving data output signals from a pair of lines, first differential output circuits, said pair of input circuits being connected to receive a first common control signal; a second differential amplifier including first input circuit for receiving a data input signal, a second input circuit for receiving a first reference input signal, second differential output circuits for generating output data signals, said first input circuit coupled to one of said pair of input circuits through one of said second differential output circuits connected to a first one of said lines, said second input circuit coupled to the other of said pair of input circuits through another of said second differential output circuits connected to a second one of said lines, said other pair of input circuits of said second differential amplifier being connected to receive a second common control signal; and, a third differential amplifier including a first input circuit for receiving a bilevel control signal, a second input circuit for receiving a second reference input signal, and first and second differential output circuits connected to apply alternately said first and second common control signals to said first and second amplifiers, respectively.

Claim 5

A differential line driver-receiver device comprising: a first differential amplifier including a pair of input circuits for receiving data output signals from a pair of lines, first differential output circuits, said pair of input circuits being connected to receive a first common control signal; a second differential amplifier including first input circuit for receiving a data input signal, a second input circuit for receiving a first reference input signal, second differential output circuits for generating output data signals, said first input circuit coupled to one of said pair of input circuits through one of said second differential output circuits connected to a first one of said lines, said second input circuit coupled to the other of said pair of input circuits through another of said second differential output circuits connected to a second one of said lines, said other pair of input circuits of said second differential amplifier being connected to receive a second common control signal; and, a third differential amplifier including a first input circuit for receiving a bilevel control signal, a second input circuit for receiving a second reference input signal, and first and second differential output circuits connected to apply alternately said first and second common control signals to said first and second amplifiers, respectively.

Claim 6

The device of claim 3 wherein said first differential amplifier means, said second differential means and said third differential amplifier means, each includes first and second amplifying transistors, each having emitter, base and collector electrodes; said first and second transistors of said first differential amplifier having said emitter electrodes connected to receive said first common control signal, input circuits connected to a different one of said base electrodes for receiving bilevel complementary data signals from said lines and one of said first differential output circuits connected to said collector electrode of said first transistor; said first and second transistors of said second differential amplifier having said emitter electrodes connected to receive said second common control signal, said first input circuit connected to said base electrode of said first transistor, said second input circuit connected to said base electrode of said second transistor, each of said second differential output circuits connected to a different one of said collector electrodes; and said first and second transistors of said third differential amplifier including said emitter electrodes connected to an enabling voltage, said input circuit of said third differential connected to the base electrode of said first transistor, said second input circuit connected to the base electrode of said second transistor, said first and second differential output circuits respectively connected to said first and second transistor collector electrodes whereby said third differential amplifier when conditioned by one level of said control signal only applies said enabling voltage corresponding to said first common control signal through the emitter and collector electrodes of said second transistor and when conditioned by the other level only applies the same enabling voltage corresponding to said common control signal through the emitter and collector electrodes of said first transistor.

Claim 7

The device of claim 4 wherein said bilevel control signal and data input signaLs are logic levels and said second and third differential amplifiers includes a level shifting means connected in series with said base electrode of each of said first transistors for receiving said data input signal and said bilevel control signal respectively and for converting said data input signal and said bilevel logic control signal to predetermined voltage levels for application to said base electrodes.

Claim 8

The device of claim 4 wherein said one of said first differential output circuits of said first differential amplifier includes slope control circuit means for producing a slope controlled logic output signal to a utilization device.

Claim 9

The device of claim 4 wherein said first reference potential has a value which lies midway between the two levels of said bilevel control signal applied to said base electrode of said first transistor of said third differential amplifier.

Claim 10

The device of claim 4 wherein said lines are a twisted two conductor pair connected in a balanced arrangement.

Claim 11

The device of claim 4 wherein one of said input circuits of said first differential amplifier includes means connected to the base electrode of one of said transistors for operating said first differential amplifier alternatively in a balanced and unbalanced line arrangement.

Claim 12

The device of claim 9 wherein said means includes a pair of jumpers and a source of reference potential, one of said jumpers connecting said base electrode to said line and the other of said jumpers connecting said base electrode to said source of reference potential wherein when connected in an unbalanced arrangement said base electrode only connects through said one jumper means to said source of reference potential.

Claim 13

A transmit-receive unit for interconnecting a utilization device to a two conductor transmission line at a single point along its length, said unit comprising: a first differential amplifier means for receiving bilevel data signals from said line conductors, said amplifier means having first and second amplifying transistors each having emitter, collector, and base electrodes, each of said base electrodes connected to a different conductor of said line, said emitter electrodes connected to a first common control circuit for receiving a first control signal and said differential amplifier means having at least one collector electrode connected to a load impedance for producing data signals in response to said bilevel data signals applied to said base electrodes from said conductors; and a second differential amplifier means for transmitting bilevel data signals to said line conductors, said second amplifier means having third and fourth amplifying transistors each having an emitter, collector, and base electrodes; said emitter electrodes connected in common to a second common control circuit for receiving a second control signal and each said collector electrodes connected in common with said base electrodes of said first differential amplifier means, one of said base electrodes connected to receive a data signal input from said utilization device and the other of said base electrodes connected to a first reference potential, and said unit responsive to the alternate application of said first and second control signals to be enabled respectively for receive and transmit modes of operation.

Claim 14

A transmit-receive unit for interconnecting a utilization device to a two conductor transmission line at a single point along its length, said unit comprising: a first differential amplifier means for receiving bilevel data signals from said line conductors, said amplifier means having first and second amplifying transistors each having emitter, collector, and base electrodes, each of said base electrodes connected to a different conductor of said line, said emitter electrodes connected to a first common control circuit for receiving a first control signal and said differential amplifier means having at least one collector electrode connected to a load impedance for producing data signals in response to said bilevel data signals applied to said base electrodes from said conductors; and a second differential amplifier means for transmitting bilevel data signals to said line conductors, said second amplifier means having third and fourth amplifying transistors each having an emitter, collector, and base electrodes; said emitter electrodes connected in common to a second common control circuit for receiving a second control signal and each said collector electrodes connected in common with said base electrodes of said first differential amplifier means, one of said base electrodes connected to receive a data signal input from said utilization device and the other of said base electrodes connected to a first reference potential, and said unit responsive to the alternate application of said first and second control signals to be enabled respectively for receive and transmit modes of operation.

Claim 15

The unit of claim 11 further including current source means; and third differential amplifier means, said third differential amplifier means including fifth and sixth amplifying transistors each having emitter, base and collector electrodes, said emitter electrodes connected to said current source means, said fifth transistor collector electrode connected to said second common control circuit and said sixth transistor collector electrode connected to said first common control circuit, said fifth transistor base electrode connected to receive a second reference signal and said sixth transistor base electrode connected to receive bilevel gate control signal wherEby said third differential amplifier means is responsive to said gate control signal to selectively connect said current source to said first and second common control circuits.

Claim 16

The unit of claim 12 wherein the amplifying transistors of said first, second and third differential amplifier means are of the same conductivity.

Claim 17

The unit of claim 12 wherein one level of said gate control signal renders only said fifth transistor conductive and said other level of said control signal renders only said sixth transistor conductive.