Method and circuit arrangement for decoding and correcting information transmitted in a convolutional code

Claim 3

A method, as claimed in claim 1, including the steps of using a first modulo-2-addeR as a first decoder to form the pairs of parity bits in the data sequence D; supplying the data sequence D to a correction member connected to the output of the first decoder; supplying the data sequence D'' to a shift register connected to the output of the correction member and differing by one place from the first-mentioned shift register and corresponding thereto from the second place of the first-mentioned shift register onwardly and having an appropriate parity-bit logical circuit consisting of further modulo-2-adders, the second-mentioned shift register constituting a second decoder; deriving two sequences of parity bits from the second-mentioned shift register; supplying the last-mentioned two sequences of parity bits and the two parity-bits of each pair, decoded with a time delay, to respective additional modulo-2-adders to form the data sequences A and B; and supplying the data sequences A and B to the comparison member for comparison therein with the data sequence D to form the data sequence D''.

Claim 4

A method, as claimed in claim 1, including the step of, when the condition ''''2'''' appears more frequently than once during a sequence including a predetermined number of input bits greater than four, supplying an error signal to a device which processes the decoded data.

Claim 5

A method, as claimed in claim 3, including the step of counting the frequency of appearance of condition ''''2'''' during each such sequence involving a predetermined number of input bits.

Claim 6

A method, as claimed in claim 3, including the step of, when the condition ''''2'''' appears more frequently than once during the sequence includina predetermined number of input bits, interrupting correction of the data contained in the correction member for a period equal to the constraint length of the convolutional code.

Claim 7

A method, as claimed in claim 4, including the step of, when the condition ''''2'''' occurs at least two times during each of two sequences including a predetermined number of input bits, delaying the data flow one bit.

Claim 8

A method, as claimed in claim 2, including the step of using the condition ''''3,'''' which necessarily follows the condition ''''2, '''' to control the appearance of the condition ''''2''''.

Claim 9

A circuit arrangement for decoding and correcting a data sequence expressed in a convolutional code, and transmitted as two sequences of parity bits generated, from the information to be coded, by respective generator matrices and which sequences are formed by modfulo-2-adders at selected places of a shift register adjusted to the constraint length of the code, the sequences differing at only one place of the shift register, said circuit arrangement comprising, in combination, a first modulo-2-adder; a correction member; a second shift register corresponding to said first-mentioned shift register and differing by one place from said first-mentioned shift register, said second shift register having two parity bit logical circuits corresponding to those of said first-mentioned shift register from the second step of said first-mentioned shift register onwardly; a first two-bit shift register receiving the data sequence bit-by-bit; a second two-bit shift register connected to said first two-bit shift register to receive therefrom from the data sequence bit-by-bit; means connecting said first modulo-2-adder to the outputs of said first two-bit shift register to receive the information content thereof; means connecting the first input of said correction member to the output of said first modulo-2-adder; respective second modulo-2-adders connecting respective outputs of said second two-bit register to respective comparison inputs of said correction member; means connecting the output of said correction member to the input of said second shift register; the decoded data being available, in accordance with a desired delay, at the output or at any place of said seconD shift register; and means connecting the parity bit logical circuits of said second shift register to the second inputs of respective second modulo-2-adders; said correction member having a logical circuit, providing for transmission of the correction member output signals to said second shift register, when the condition D'' (AB + BA) D + AB is fulfilled, in which D is the output signal of said first modulo-2-adder and A and B are signals supplied to the respective comparison inputs of said correction member.

Claim 10

A circuit arrangement for decoding and correcting a data sequence expressed in a convolutional code, and transmitted as two sequences of parity bits generated, from the information to be coded, by respective generator matrices and which sequences are formed by modfulo-2-adders at selected places of a shift register adjusted to the constraint length of the code, the sequences differing at only one place of the shift register, said circuit arrangement comprising, in combination, a first modulo-2-adder; a correction member; a second shift register corresponding to said first-mentioned shift register and differing by one place from said first-mentioned shift register, said second shift register having two parity bit logical circuits corresponding to those of said first-mentioned shift register from the second step of said first-mentioned shift register onwardly; a first two-bit shift register receiving the data sequence bit-by-bit; a second two-bit shift register connected to said first two-bit shift register to receive therefrom from the data sequence bit-by-bit; means connecting said first modulo-2-adder to the outputs of said first two-bit shift register to receive the information content thereof; means connecting the first input of said correction member to the output of said first modulo-2-adder; respective second modulo-2-adders connecting respective outputs of said second two-bit register to respective comparison inputs of said correction member; means connecting the output of said correction member to the input of said second shift register; the decoded data being available, in accordance with a desired delay, at the output or at any place of said seconD shift register; and means connecting the parity bit logical circuits of said second shift register to the second inputs of respective second modulo-2-adders; said correction member having a logical circuit, providing for transmission of the correction member output signals to said second shift register, when the condition D'' (AB + BA) D + AB is fulfilled, in which D is the output signal of said first modulo-2-adder and A and B are signals supplied to the respective comparison inputs of said correction member.

Claim 11

A circuit arrangement, as claimed in claim 8, including circuit means supplying thereto a timing pulse sequence corresponding to the bit rate of the signal to be decoded; a flip-flop having said timing pulse sequence supplied to its input, and having a pair of alternately switched outputs whereby, at each output, there is available a second timing pulse sequence having a frequency of one half the frequency of the input timing pulse sequence, with the two second timing pulse sequences being in 180* phase opposition to each other; a respective AND element connected to each output of said flip-flop; whereby, at the two AND elements, respective timing pulse sequences, having a relative displacement of 180*, are available so that a selected one of the two timing pulse sequences can serve for the timing pulse control of said first and second two bit shift registers.

Claim 12

A circuit arrangement, as claimed in claim 9, including a counter triggered by said second timing pulse sequences and effective to count up to a certain number of bits which may be freely chosen and which is greater than four; and means operable to reset said counter within each run of said counter as soon as the condition A B not = D appears for the second time in the same run of said counter.

Claim 13

A circuit arrangement, as claimed in claim 10, in which, in order to count, in addition, the bits which may be introduced into said second shift register, said counter is able to count at least up to a number equal to the constraint length of the used code less 1.

Claim 14

A circuit arrangement, as claimed in claim 10, comprising a second flip-flop; means connecting the input of said second flip-flop to said correction member to supply, to the input of said second flip-flop, a signal responsive to the condition A not = B; a third flip-flop having its input connected to one output of said second flip-flop; said correction member having an inhibit input blocking correction action thereof; and means connecting one output of said third flip-flop to said inhibit input.