US3840816A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wheel speed signal processing circuit for wheel slip control systems
Assignee: Echlin Inc
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Filing: 1973-03-13
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Granted: 1974-10-08
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Expires: 1993-03-13
Abstract
Abstract A control system for varying the pressure applied to fluidcontrolled brake actuating mechanisms upon detection of both a wheel deceleration in excess of a predetermined threshold and a subsequent incremental decrease in wheel velocity greater than a continuously-varying reference increment Delta v of wheel speed. This reference increment Delta v is inversely related to a variable reference signal which is directly related to the rate of change of wheel speed. Thus, the continuously-varying reference increment of wheel speed Delta v is inversely related to the rate of change of wheel speed. Consequently, the period of time between occurrence of a wheel deceleration in excess of said predetermined threshold and the relief of brake line fluid pressure is shorter when wheel speed decreases rapidly and longer when wheel speed decreases slowly. Compensation is thus made for varying road and load conditions, and for the characteristics of the braking mechanism which applies braking force to the wheel.
Inventors
- 👤 J Fleagle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 09:57
CPC Classifications
B; B60; B60T; B60T8/00; B60T8/17; B60T8/176; B60T8/1763; B60T8/17633; B60T8/32; B60T8/34; B60T8/36; B60T8/361; G; G01; G01P; G01P1/00; G01P1/07; G01P1/08; G01P1/10; G01P1/103; G01P15/00; G01P15/02; G01P15/08; G01P15/0891; G01P15/16; G01P3/00; G01P3/42; G01P3/56
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
79 words
A signal-processing circuit comprising: 1. first circuit means operative to generate a first variablewidth pulse whenever the first derivative of an input signal exceeds a first reference signal; 2. second circuit means operative to generate a second variablewidth pulse whenever said input signal falls below a second, continuously variable reference signal after initiation of said first variable-width pulse; and 3. third circuit means operative to generate a variable-width output pulse in response to at least said second variable-width pulse.
Claim 2
Dependent Claim
79 words
A signal-processing circuit comprising: 1. first circuit means operative to generate a first variablewidth pulse whenever the first derivative of an input signal exceeds a first reference signal; 2. second circuit means operative to generate a second variablewidth pulse whenever said input signal falls below a second, continuously variable reference signal after initiation of said first variable-width pulse; and 3. third circuit means operative to generate a variable-width output pulse in response to at least said second variable-width pulse.
Claim 3
Dependent Claim
30 words
second circuit means operative to generate a second variable-width pulse whenever said input signal falls below a second, continuously variable reference signal after initiation of said first variable-width pulse; and
Claim 4
Dependent Claim
30 words
second circuit means operative to generate a second variable-width pulse whenever said input signal falls below a second, continuously variable reference signal after initiation of said first variable-width pulse; and
Claim 5
Dependent Claim
24 words
first threshold circuit means operative to generate said first variable-width pulse whenever said first derivative of said input signal exceeds said first reference signal.
Claim 6
Dependent Claim
24 words
first threshold circuit means operative to generate said first variable-width pulse whenever said first derivative of said input signal exceeds said first reference signal.
Claim 7
Dependent Claim
24 words
The circuit according to claim 1 wHerein said second, continuously variable reference signal is directly related to said first derivative of said input signal.
Claim 8
Dependent Claim
28 words
timer means operative in response to initiation of said second variable-width to generate an output for a predetermined period of time after initiation of said second variable-width pulse;
Claim 9
Dependent Claim
28 words
timer means operative in response to initiation of said second variable-width to generate an output for a predetermined period of time after initiation of said second variable-width pulse;
Claim 10
Dependent Claim
27 words
second logic means operative to generate said variable-width output in response to either said second variable-width pulse output from said second comparison means or the output from
Claim 11
Dependent Claim
27 words
second logic means operative to generate said variable-width output in response to either said second variable-width pulse output from said second comparison means or the output from
Claim 12
Dependent Claim
37 words
first logic means operative in response to either said first variable-width pulse or said first output of said timer means to cause said gating circuit means to pass said input signal to said second threshold circuit means.
Claim 13
Dependent Claim
37 words
first logic means operative in response to either said first variable-width pulse or said first output of said timer means to cause said gating circuit means to pass said input signal to said second threshold circuit means.
Claim 14
Dependent Claim
37 words
second threshold circuit means operative to compare said input signal to said second, continuously variable reference signal and to generate said second variable-width pulse whenever said input signal falls below said second, continuously variable reference signal; and
Claim 15
Dependent Claim
37 words
second threshold circuit means operative to compare said input signal to said second, continuously variable reference signal and to generate said second variable-width pulse whenever said input signal falls below said second, continuously variable reference signal; and
Claim 16
Dependent Claim
57 words
third logic means operative in response to the coincidence of a second output from said timer means, a third variable-width pulse output from said third comparison means, and an output from said second logic means to extend the output of said second logic means after termination of said second variable-width pulse output from said second comparison means.
Claim 17
Dependent Claim
57 words
third logic means operative in response to the coincidence of a second output from said timer means, a third variable-width pulse output from said third comparison means, and an output from said second logic means to extend the output of said second logic means after termination of said second variable-width pulse output from said second comparison means.
Claim 18
Dependent Claim
24 words
variable reference signal generator means operative to receive said first derivative of said input signal and to generate said second, continuously variable reference signal.
Claim 19
Dependent Claim
24 words
variable reference signal generator means operative to receive said first derivative of said input signal and to generate said second, continuously variable reference signal.
Claim 20
Dependent Claim
27 words
second logic means operative to generate said variable-width output in response to either said second variable-width pulse output from said second comparison means or the output from
Claim 21
Dependent Claim
27 words
second logic means operative to generate said variable-width output in response to either said second variable-width pulse output from said second comparison means or the output from
Claim 22
Dependent Claim
19 words
third circuit means operative to generate a variable-width output pulse in response to at least said second variable-width pulse.
Claim 23
Dependent Claim
19 words
third circuit means operative to generate a variable-width output pulse in response to at least said second variable-width pulse.
Claim 24
Dependent Claim
12 words
The circuit according to claim 1 wherein said first circuit means comprises:
Claim 25
Dependent Claim
56 words
third logic means operative in response to the coincidence of said output from said timer means, said third variable-width pulse output from said comparison means, and said variable-width output from said second logic means to extend the output of said second logic means after termination of said second variable-width pulse output from said second comparison means.
Claim 26
Dependent Claim
56 words
third logic means operative in response to the coincidence of said output from said timer means, said third variable-width pulse output from said comparison means, and said variable-width output from said second logic means to extend the output of said second logic means after termination of said second variable-width pulse output from said second comparison means.
Claim 27
Dependent Claim
12 words
The circuit according to claim 3 wherein said second circuit means comprises:
Claim 28
Dependent Claim
13 words
The circuit according to claim 4 wherein said second circuit means further comprises:
Claim 29
Dependent Claim
12 words
The circuit according to claim 5 wherein said third circuit means comprises:
Claim 30
Dependent Claim
24 words
The circuit according to claim 6 wherein said second logic means comprises an OR gate, and said third logic means comprises an AND gate.
Claim 31
Dependent Claim
28 words
The circuit according to claim 6 wherein said third circuit means further comprises power amplifier means operative to receive and amplify said output from said second logic means.
Claim 32
Dependent Claim
12 words
The circuit according to claim 1 wherein said third circuit means comprises:
Claim 33
Dependent Claim
24 words
The circuit according to claim 9 wherein said second logic means comprises an OR gate, and said Third logic means comprises an AND gate.
Claim 34
Dependent Claim
28 words
The circuit according to claim 9 wherein said third circuit means further comprises power amplifier means operative to receive and amplify said output from said second logic means.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-10-07 | 1978-04-08 | 1978-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-10-07 | 1982-04-08 | 1982-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-10-07 | 1986-04-08 | 1986-10-08 | $7700.00 | Window Closed / Lapsed |