US3840707A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Intermediate exchange for digital signals,for connection of one of a number of inlets to a specific outlet of a number of outlets
Assignee: Telefonaktiebolaget LM Ericsson AB
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Filing: 1972-12-18
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Granted: 1974-10-08
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Expires: 1992-12-18
Abstract
Abstract An intermediate exchange for digital signals, especially PCMsignals has a number of inlets (incoming links) and an equal number of outlets (outgoing links) which are time- and spacedivided. For each inlet to the exchange a storage block is provided which comprises a number of link address registers for storing the value of the desired outgoing link, a number of channel address registers for storing the value of the desired channel in the outgoing link and a binary information word register for storing the value of the PCM-word. The number of the respective registers is equal and equal to the number of channels of each inlet to the exchange. A stepping clock counts the address values of the channels sequentially and a clock address value together with the value of a channel address register are compared and upon coincidence the value of the associated link address register together with the value of the associated information word register are fed to a decoder for delivering the information word, for example, the PCM-word to the desired outlet (outgoing link).
Inventors
- 👤 G Hemdal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:00
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/06
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
337 words
In a telecommunication system transmitting pulse code modulated time division multiplex signals, an intermediate exchange connecting arbitrary incoming pulse time position channels on incoming links with arbitrary outgoing pulse time position channels on outgoing links, said intermediate exchange comprising: a plurality of storage means, each of said storage means being connected to a different one of said incoming links, each of said storage means having a storage position for each of the incoming channels of the link, each of said storage positions having a first register for storing a pulse coded modulated binary information word, a second register for storing the address of the desired outgoing link for the associated binary information word and third register for storing the address of the desired outgoing channel for the associated binary information word; marker means for loading the desired outgoing link address and the desired outgoing channel addresses in the respective second and third registers; a clock register means for sequentially and cyclically generating each of the possible channel addresses; a plurality of channel address comparator circuits, each of said channel address comparator circuits having a first inlet connected to said clock register means and a second inlet connected to one of said third registers for storing a desired channel address whereby each third register of each link is connected to a different comparator circuit, each of said channel address comparator circuits including means for generating an activation signal upon detecting a predetermined relationship between the address received for said clock register means and the address stored in the associated third register; a plurality of selectively activatable decoder means, each of said decoder means being connected to one of said channel address comparator circuits for receiving activation signals therefrom and being connected to the first and second register associated with said channel address comparator circuit, each of said decoder means including means when activated for transferring the information word of its associated fIrst register to an outgoing link indicated by the address word stored in its associated second register.
Claim 2
Dependent Claim
337 words
In a telecommunication system transmitting pulse code modulated time division multiplex signals, an intermediate exchange connecting arbitrary incoming pulse time position channels on incoming links with arbitrary outgoing pulse time position channels on outgoing links, said intermediate exchange comprising: a plurality of storage means, each of said storage means being connected to a different one of said incoming links, each of said storage means having a storage position for each of the incoming channels of the link, each of said storage positions having a first register for storing a pulse coded modulated binary information word, a second register for storing the address of the desired outgoing link for the associated binary information word and third register for storing the address of the desired outgoing channel for the associated binary information word; marker means for loading the desired outgoing link address and the desired outgoing channel addresses in the respective second and third registers; a clock register means for sequentially and cyclically generating each of the possible channel addresses; a plurality of channel address comparator circuits, each of said channel address comparator circuits having a first inlet connected to said clock register means and a second inlet connected to one of said third registers for storing a desired channel address whereby each third register of each link is connected to a different comparator circuit, each of said channel address comparator circuits including means for generating an activation signal upon detecting a predetermined relationship between the address received for said clock register means and the address stored in the associated third register; a plurality of selectively activatable decoder means, each of said decoder means being connected to one of said channel address comparator circuits for receiving activation signals therefrom and being connected to the first and second register associated with said channel address comparator circuit, each of said decoder means including means when activated for transferring the information word of its associated fIrst register to an outgoing link indicated by the address word stored in its associated second register.
Claim 3
Dependent Claim
83 words
The intermediate exchange of claim 1 wherein each of said channel address comparator circuits includes means for performing an EXCLUSIVE-OR operation between the channel addresses from said clock register means and the channel address stored in the associated third register, said activation signal appearing on the outlet of said channel address comparator circuit if the two addresses are identical, and a logic AND-circuit controlled by said activation signal for passing the contents of the associated first and second registers to said decoder means.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-10-07 | 1978-04-08 | 1978-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-10-07 | 1982-04-08 | 1982-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-10-07 | 1986-04-08 | 1986-10-08 | $7700.00 | Window Closed / Lapsed |