Hybrid interfacing of computational functions in a hybrid loadflow computer arrangement for electric power systems

Claim 2

A hybrid loadflow computer arrangement comprising a DC analog simulator of an AC network, said simulator including a plurality of bus DC circuits and line DC circuits interconnected to correspond to the AC network, a digital computer including means for determining bus generation and load currents as a function of predetermined parameters including stored bus power and voltage data, an analog output system, said digital computer including means for causing said output system to generate phasor current signals representative of the digital computer determined bus bus generation and lOad currents, each of said bus DC circuits including means for responding to line phasor current and bus generation and load phasor input current signals and for generating an output bus voltage phasor signal, each of said line DC circuits including means for responding to the difference between applied bus voltage phasor signals and generating an output line phasor current signal in accordance with a representation of the equivalent series branch line impedance, said digital computer including: means for determining and storing representations of bus voltage phasor signals after the generation and load phasor current signals are applied to said DC bus circuits, means for determining bus generation and load currents in successive iterations as a function of bus voltage values determined in the next preceding iteration, means for converging the solution, means for determining when a solution is reached, means for determining line charging currents for connected DC line circuits in said analog simulator, means for causing said output system to generate phasor current signals representative of both the bus generation and load currents and the line charging currents; and means for applying the phasor current signals to predetermined simulator circuit points including bus DC circuit inputs.

Claim 3

A hybrid loadflow computer as set forth in claim 1 wherein the line charging currents are algebraically summed with corresponding bus generation and load currents and the resultant output bus current phasor signals are applied to the corresponding bus DC circuit inputs.

Claim 4

A hybrid loadflow computer as set forth in claim 2 wherein each line charging current is calculated from the applicable bus voltage and the applicable representation of the series branch equivalent impedance.

Claim 5

A hybrid loadflow computer arrangement comprising a DC analog simulator of an AC network, said simulator including a plurality of bus DC circuits and line DC circuits interconnected to correspond to the AC network, a digital computer including means for determining bus generation and load currents as a function of predetermined parameters including stored bus power and voltage data, an analog output system, said digital computer including means for causing said output system to generate phasor current signals representative of the digital computer determined bus generation and load currents, each of said bus DC circuits including means for responding to line phasor current and bus generation and load phasor input current signals and for generating an output bus voltage phasor signal, each of said line DC circuits including means for responding to the difference between applied bus voltage phasor signals and generating an output line phasor current signal in accordance with a representation of the equivalent series branch line impedance, said computer including means for: determining and storing representations of bus voltage phasor signals after the generation and load phasor current signals are applied to said DC bus circuits, means for determining bus generation and load currents in successive iterations as a function of bus voltage values determined in the next preceding iteration, means for converging the solution, means for determining when a solution is reached, means for determining as a function of off-nominal turns ratio a representation of transformer impedance compensation for the leg circuits of Pi equivalents of transformers represented in said analog simulator, means for causing said output system to generate phasor current signals representative of both the bus generation and load currents and the line charging currents and transformer tap ratio compensation; and means for applying the phasor current signals to predetermined simulator circuit points including bus DC circuit inputs.

Claim 6

A hybrid loadflow computer arrangement comprising a DC analog simulator of an AC network, said simulator including a plurality of bus DC circuits and line DC circuits interconnected to correspond to the AC network, a digital computer including means for determining bus generation and load currents as a function of predetermined parameters including stored bus power and voltage data, an analog output system, said digital computer including means for causing said output system to generate phasor current signals representative of the digital computer determined bus generation and load currents, each of said bus DC circuits including means for responding to line phasor current and bus generation and load phasor input current signals and for generating an output bus voltage phasor signal, each of said line DC circuits including means for responding to the difference between applied bus voltage phasor signals and generating an output line phasor current signal in accordance with a representation of the equivalent series branch line impedance, said computer including means for: determining and storing representations of bus voltage phasor signals after the generation and load phasor current signals are applied to said DC bus circuits, means for determining bus generation and load currents in successive iterations as a function of bus voltage values determined in the next preceding iteration, means for converging the solution, means for determining when a solution is reached, means for determining as a function of off-nominal turns ratio a representation of transformer impedance compensation for the leg circuits of Pi equivalents of transformers represented in said analog simulator, means for causing said output system to generate phasor current signals representative of both the bus generation and load currents and the line charging currents and transformer tap ratio compensation; and means for applying the phasor current signals to predetermined simulator circuit points including bus DC circuit inputs.

Claim 7

A hybrid loadflow computer as set forth in claim 4 wherein the turns ratio compensation is determined as a representation of equivalent leg admittance and the bus geneRation and load current values reflect compensatory bus currents corresponding to the equivalent leg admittance representation at transformer connected busses.

Claim 8

A hybrid loadflow computer as set forth in claim 5 wherein said analog simulator includes modular circuits for representing transformers, each of said transformer modular circuits comprising a first circuit for generating at least one output current phasor signal corresponding to a first coordinate component of equivalent series branch current for the actual transformer, a second circuit for generating at least one other output current phasor signal corresponding to a second coordinate component of equivalent series branch current for the actual transformer, each of said circuits including means for receiving respective input phasor voltage signals corresponding to one of the two coordinate components of respective voltages at busses connected to the transformer series branch equivalent in correspondence with the actual power system, and means for representing at least the series branch portion of the transformer equivalent impedance in said first and second circuits so as to generate said output current phasor signals with the described correspondence.

Claim 9

A hybrid loadflow computer as set forth in claim 5 wherein said digital computer further includes means for determining line charging currents for connected DC line circuits in said analog simulator, and means for generating phasor current signals representative of the algebraic sum of bus generation and load currents and line charging currents and compensatory transformer equivalent admittance leg currents, and wherein the resultant output bus current phasor signals are applied to the corresponding bus DC circuit inputs.

Claim 10

A modular circuit for representing an electric power system transformer comprising a first circuit for generating at least one output current phasor signal corresponding to a first coordinate component of equivalent series branch current for the actual transformer, a second circuit for generating at least one other output current phasor signal corresponding to a second coordinate component of equivalent series branch current for the actual transformer, each of said circuits including means for receiving respective input phasor voltage signals corresponding to one of the two coordinate components of respective voltages at busses connected to the transformer series branch equivalent in correspondence with the actual power system, and means for representing at least the series branch portion of the transformer equivalent impedance in said first and second circuits so as to generate said output current phasor signals with the described correspondence.

Claim 11

A modular circuit for representing an electric power system transformer comprising a first circuit for generating at least one output current phasor signal corresponding to a first coordinate component of equivalent series branch current for the actual transformer, a second circuit for generating at least one other output current phasor signal corresponding to a second coordinate component of equivalent series branch current for the actual transformer, each of said circuits including means for receiving respective input phasor voltage signals corresponding to one of the two coordinate components of respective voltages at busses connected to the transformer series branch equivalent in correspondence with the actual power system, and means for representing at least the series branch portion of the transformer equivalent impedance in said first and second circuits so as to generate said output current phasor signals with the described correspondence.

Claim 12

A modular circuit as set forth in claim 8 wherein means are provided for opening and closing the circuit continuity between the input and output of each of said first and second circuits.

Claim 13

A modular circuit as set forth in claim 8 wherein each of said circuits includes an output summing amplifier for generating the associated output current phasor signal, each of said circuits includes a comparator amplifier for generating a signal corresponding to the difference between the two input phasor voltage signals, the outputs of said comparator amplifiers are coupled to the input of said output amplifiers in said first circuit, an inverter is provided for inverting the output of said comparator amplifier in said first circuit, and the output of said comparator amplifier in said second circuit and the output of said inverter are coupled to the input of said output amplifier in said second circuit.

Claim 14

A modular circuit as set forth in claim 10 wherein said impedance representing means include a gain resistor corresponding to equivalent transformer series line conductance connected in said first circuit between its comparator and output amplifiers, a gain resistor corresponding to equivalent transformer series line conductance is connected in said second circuit between its comParator and output amplifiers, a gain resistor corresponding to equivalent transformer series line susceptance is connected between the output of said second circuit comparator amplifier and the input of said first circuit output amplifier, and a gain resistor corresponding to equivalent transformer series line susceptance is connected between the output of said inverter and the input of said second circuit output amplifier.

Claim 15

A hybrio loadflow computer arrangement comprising a DC analog simulator of an AC network, said simulator including a plurality of bus DC circuits and line DC circuits interconnected to correspond to the AC network, a digital computer including means for determining bus generation and load currents as a function of predetermined parameters including stored bus power and voltage data, an analog output system, said digital computer further including means for causing said output system to generate phasor current signals representative of the digital computer determined bus generation and load currents, each of said bus DC circuits including means for responding to line phasor current and bus generation and load phasor input current signals and for generating an output bus voltage phasor signal, each of said line DC circuits including means for responding to the difference between applied bus voltage phasor signals and generating an output line phasor current signal in accordance with a representation of the equivalent series branch line impedance, said digital computer further including: means for determining and storing representations of bus voltage phasor signals after the generations and load phasor current signals are applied to said DC bus circuits, means for determining bus generation and load currents in successive iterations as a function of bus voltage values determined in the next preceding iteration, means for converging the solution, means for determining when a solution is reached, means for operating said output system to generate phasor current signals representative of bus generation and load and line charging currents, means for applying the phasor current signals to predetermined simulator circuit points including bus DC circuit inputs; at least one of the simulator bus circuits is selected as a slack bus circuit, means are provided for holding the slack bus output voltage phasor signals at a reference value with the slack voltage referenced to ground and with all of said bus and line circuits formed substantially without any circuit path coupling to ground other than through the slack bus.

Claim 16

A hybrio loadflow computer arrangement comprising a DC analog simulator of an AC network, said simulator including a plurality of bus DC circuits and line DC circuits interconnected to correspond to the AC network, a digital computer including means for determining bus generation and load currents as a function of predetermined parameters including stored bus power and voltage data, an analog output system, said digital computer further including means for causing said output system to generate phasor current signals representative of the digital computer determined bus generation and load currents, each of said bus DC circuits including means for responding to line phasor current and bus generation and load phasor input current signals and for generating an output bus voltage phasor signal, each of said line DC circuits including means for responding to the difference between applied bus voltage phasor signals and generating an output line phasor current signal in accordance with a representation of the equivalent series branch line impedance, said digital computer further including: means for determining and storing representations of bus voltage phasor signals after the generations and load phasor current signals are applied to said DC bus circuits, means for determining bus generation and load currents in successive iterations as a function of bus voltage values determined in the next preceding iteration, means for converging the solution, means for determining when a solution is reached, means for operating said output system to generate phasor current signals representative of bus generation and load and line charging currents, means for applying the phasor current signals to predetermined simulator circuit points including bus DC circuit inputs; at least one of the simulator bus circuits is selected as a slack bus circuit, means are provided for holding the slack bus output voltage phasor signals at a reference value with the slack voltage referenced to ground and with all of said bus and line circuits formed substantially without any circuit path coupling to ground other than through the slack bus.

Claim 21

A method as set forth in claim 14 wherein the steps further comprise operating said digital computer to determine line charging currents for connected DC line circuits in said analog simulator, operating said digital computer to cause said output system to generate phasor current signals representative of the bus generation and load currents and the line charging currents and compensatory transformer equivalent admittance leg currents.