US3835387A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Control circuitry for information transmission system
Assignee: Columbia Pictures Industries Inc
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Filing: 1972-11-15
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Granted: 1974-09-10
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Expires: 1992-11-15
Abstract
Abstract Logic circuitry for control of advisable converter-tuner stations of a cable television distribution system. The converter-tuners of the system are controlled by logic circuitry responsive to tone bursts modulated on a command carrier. The logic circuitry employs retriggerable one shot element to transform the logical bits of the command signal comprising tones into a clock signal and separate data signal, the clock signal being coherent with the data. The data in the tone bursts are encoded on a command carrier in a split phase mark mode, groups of such tones constituting a command word having address and command portions. A read only memory is used to internally generate the address of the converter receiving the command signal. Comparison circuitry is provided in order that the actual address received may be compared with the internally generated address to determine whether the unit receiving the address is in fact receiving its own address. This serial bit-by-bit comparison halts the further execution of the program by the unit at the first mismatch of an address bit. The read only memory also provides signals to control the response of the unit to the command portion of the command message in the event that the unit receiving the command message is the one addressed by the address portion thereof. A data presence detector automatically resets the system on the expiration of the command word transmission.
Inventors
- 👤 E Rooks
- 👤 D Lewis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:30
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/16; H04N7/173; H04N7/17345; H04N7/17363; H04N2007/1739
Claims Analysis
Total Claims: 43
Claim 1
Independent Claim
190 words
Apparatus for decoding a coded signal having a first serial bit pattern forming one of a plurality of different address signals, one of said plurality of address signals corresponding to said apparatus, said apparatus comprising: a. means responsive to the first serial bit pattern for providing a second serial bit pattern corresponding to the first serial bit pattern of the one address signal, the second serial bit pattern thereby corresponding to the one of the plurality of address signals corresponding to said apparatus, b. means for comparing the second serial bit pattern to the first serial bit pattern of the one address signal by serially comparing the bits of the second serial bit pattern with each of the corresponding bits of the first serial bit pattern of the predetermined one address signal to determine matching between the second serial bit pattern and the one address signal, and c. means responsive to said determination of matching by said comparing means for producing a control signal, whereby said apparatus delivers the control signal only when the one address signal of the plurality of the different address signals is received by said apparatus.
Claim 2
Dependent Claim
190 words
Apparatus for decoding a coded signal having a first serial bit pattern forming one of a plurality of different address signals, one of said plurality of address signals corresponding to said apparatus, said apparatus comprising: a. means responsive to the first serial bit pattern for providing a second serial bit pattern corresponding to the first serial bit pattern of the one address signal, the second serial bit pattern thereby corresponding to the one of the plurality of address signals corresponding to said apparatus, b. means for comparing the second serial bit pattern to the first serial bit pattern of the one address signal by serially comparing the bits of the second serial bit pattern with each of the corresponding bits of the first serial bit pattern of the predetermined one address signal to determine matching between the second serial bit pattern and the one address signal, and c. means responsive to said determination of matching by said comparing means for producing a control signal, whereby said apparatus delivers the control signal only when the one address signal of the plurality of the different address signals is received by said apparatus.
Claim 3
Dependent Claim
126 words
Apparatus in accordance with claim 1 in which said means for comparing the second serial bit pattern to the first serial bit pattern to determine matching therewith comprises: a. an exclusive OR gate having an input connected to receive the serial bit patterns of the one address signal and a second input to receive the second serial bit pattern from said means for providing the second serial bit pattern, said exclusive OR gate in response to the matching of each of the corresponding serial bits of the one address signal and second serial bit patterns at each of its inputs delivering a common output signal; and b. means responsive to a pattern of common output signals from said exclusive OR gate for providing a control signal.
Claim 4
Dependent Claim
42 words
Apparatus in accordance with claim 1 in which said means responsive to the one address signal for providing the second serial bit pattern corresponding in format to the first serial bit pattern of the one address signal comprises a read only memory.
Claim 5
Dependent Claim
110 words
ApparatuS for decoding a coded signal in accordance with claim 1 and further comprising: a. means connected to said comparing means and responsive to the absence of matching of any portion of the second serial bit pattern to the corresponding portion of the first serial bit pattern of the one address signal for providing a terminating signal; and b. means responsive to the occurrence of the terminating signal for interrupting the decoding by said apparatus, whereby the apparatus is prevented from continuing to decode an address signal having a serial bit pattern which does not match the second serial bit pattern constituting the one address which corresponds to said apparatus.
Claim 6
Dependent Claim
27 words
Apparatus in accordance with claim 4 and further comprising means responsive to the determination of matching for actuating said apparatus to decode a subsequent serial bit pattern.
Claim 7
Dependent Claim
76 words
Apparatus in accordance with claim 1 in which said means for providing a second serial bit pattern corresponding in format to the first serial bit pattern of the one address signal is also responsive to a special predetermined address unrelated to said apparatus and different from each of the plurality of address signals, said comparing means further actuating said control signal producing means to produce said control signal upon the occurrence of the special address signal.
Claim 8
Dependent Claim
160 words
Apparatus for decoding a coded signal having a first serial bit pattern forming one of a plurality of different address signals, one address signal of said plurality corresponding to said apparatus, and another serial bit pattern forming a command signal said apparatus comprising: a. means responsive to the occurrence of the first serial bit pattern for providing a second serial bit pattern corresponding to the first serial bit pattern; ; b. means for comparing the first and second serial bit patterns to determine matching therebetween; c. means connected to said comparing means and being responsive to said determination of matching for producing an enabling signal; d. means responsive to the occurrence of the enabling signal for actuating said apparatus to decode the serial bit pattern of the command signal; and e. means connected to said command decoding actuation means for providing a second control signal in response to and which is a function of said decoding of said command signal.
Claim 9
Dependent Claim
160 words
Apparatus for decoding a coded signal having a first serial bit pattern forming one of a plurality of different address signals, one address signal of said plurality corresponding to said apparatus, and another serial bit pattern forming a command signal said apparatus comprising: a. means responsive to the occurrence of the first serial bit pattern for providing a second serial bit pattern corresponding to the first serial bit pattern; ; b. means for comparing the first and second serial bit patterns to determine matching therebetween; c. means connected to said comparing means and being responsive to said determination of matching for producing an enabling signal; d. means responsive to the occurrence of the enabling signal for actuating said apparatus to decode the serial bit pattern of the command signal; and e. means connected to said command decoding actuation means for providing a second control signal in response to and which is a function of said decoding of said command signal.
Claim 10
Dependent Claim
43 words
Apparatus in accordance with claim 7 in which said means for comparing the first and second serial bit patterns serially compares each of the bits of the second serial bit pattern with each of the corresponding bits of the first serial bit pattern.
Claim 11
Dependent Claim
112 words
Apparatus in accordance with claim 8 in which said means for comparing the first and second serial bit pattern comprises: a. an exclusive OR gate having an input connected to receive the first serial bit patterns and a second input to receive the second serial bit patterns from said means for providing a second serial bit pattern, said exclusive OR gate in response to the correspondence of each of the serial bits of the first and second serial bit patterns at each of its inputs delivering a common output signal; and b. means responsive to a pattern of common output signals from said exclusive OR gate for providing a second control signal.
Claim 12
Dependent Claim
36 words
Apparatus in accordance with claim 7 in which said means responsive to the first serial bit pattern for providing a second serial bit pattern corresponding to the first serial bit pattern comprises a read only memory.
Claim 13
Dependent Claim
91 words
Apparatus for decoding a coded signal in accordance with claim 7 and further comprising: a. means connected to said comparing means and responsive to the absence of correspondence of any portion of the second serial bit pattern to the first serial bit pattern for providing a terminating signal; and b. means responsive to the occurrence of the terminating signal for interrupting the decoding by said apparatus, whereby the apparatus is prevented from continuing to decode A coded signal having a first serial bit pattern which does not form the one address.
Claim 14
Dependent Claim
33 words
Apparatus in accordance with claim 11 further comprising means responsive to the end of first serial bit pattern following said terminating signal for reactivating said apparatus to decode a later occurring coded signal.
Claim 15
Dependent Claim
58 words
Apparatus in accordance with claim 7 in which said means responsive to the first serial bit pattern for providing a second serial bit pattern is also responsive to a special predetermined address signal unrelated to said apparatus and different from the one address, said comparing means providing said enabling signal upon the occurrence of the special predetermined address.
Claim 16
Dependent Claim
120 words
In a remotely controlled communication system apparatus for decoding a coded signal having a first serial bit pattern forming one of a plurality of predetermined address signals, said one address signal being related to said apparatus, on improvement comprising: a. means responsive to the first serial bit pattern for providing a second serial bit pattern corresponding to the one address of the first serial bit pattern; b. means for comparing the second serial bit pattern to the first serial bit pattern to determine correspondence therewith; and c. means responsive to the determination of the correspondence by said comparing means for producing a control signal, whereby said apparatus delivers a control signal only upon the occurrence of the one address signal.
Claim 17
Dependent Claim
120 words
In a remotely controlled communication system apparatus for decoding a coded signal having a first serial bit pattern forming one of a plurality of predetermined address signals, said one address signal being related to said apparatus, on improvement comprising: a. means responsive to the first serial bit pattern for providing a second serial bit pattern corresponding to the one address of the first serial bit pattern; b. means for comparing the second serial bit pattern to the first serial bit pattern to determine correspondence therewith; and c. means responsive to the determination of the correspondence by said comparing means for producing a control signal, whereby said apparatus delivers a control signal only upon the occurrence of the one address signal.
Claim 18
Dependent Claim
146 words
In a remotely controlled communication system apparatus for decoding a coded signal having a first serial bit pattern forming one of a plurality of address signals, one of said plurality of address signals being related to said apparatus and another serial bit pattern forming a command signal an improvement comprising: a. means responsive to the first serial bit pattern for providing a second serial bit pattern corresponding to the first serial bit pattern; b. means for comparing the second serial bit pattern to the first serial bit pattern to determine correspondence therebetween; c. means responsive to the determination of the correspondence by said comparing means for producing an enabling signal; d. means responsive to the occurrence of the enabling signal for decoding the serial bit pattern of the command signal; and e. means for providing a second control signal in response to the decoded command signal.
Claim 19
Dependent Claim
146 words
In a remotely controlled communication system apparatus for decoding a coded signal having a first serial bit pattern forming one of a plurality of address signals, one of said plurality of address signals being related to said apparatus and another serial bit pattern forming a command signal an improvement comprising: a. means responsive to the first serial bit pattern for providing a second serial bit pattern corresponding to the first serial bit pattern; b. means for comparing the second serial bit pattern to the first serial bit pattern to determine correspondence therebetween; c. means responsive to the determination of the correspondence by said comparing means for producing an enabling signal; d. means responsive to the occurrence of the enabling signal for decoding the serial bit pattern of the command signal; and e. means for providing a second control signal in response to the decoded command signal.
Claim 20
Dependent Claim
204 words
Apparatus for decoding a coded signal transmitted thereto, the coded signal bearing information represented by the occurrence in the signal of at least one of a plurality of conditions within each of a succession of defined bit cells, said information including a first serial bit pattern said apparatus comprising: a. means for detecting the coded signal; b. means for storing a predetermined signal, the predetermined signal comprising a second serial bit patter having bit cells corresponding to at least some of the bit cells of the first serial bit pattern of the coded signal; c. generation means connected to said storing means for causing said storing means to generate the predetermined signal; d. means connected to said storing means and to said detecting means for successively comparing the respective conditions of the second serial bit pattern of the predetermined signal with the respective states of the first serial bit pattern of the coded signal; and e. means connected to said comparing means and being responsive to a predetermined relation between the states of the second serial bit pattern of the predetermined signal and the first serial bit pattern of the coded signal for producing an output signal to interrupt the operation of the apparatus.
Claim 21
Dependent Claim
204 words
Apparatus for decoding a coded signal transmitted thereto, the coded signal bearing information represented by the occurrence in the signal of at least one of a plurality of conditions within each of a succession of defined bit cells, said information including a first serial bit pattern said apparatus comprising: a. means for detecting the coded signal; b. means for storing a predetermined signal, the predetermined signal comprising a second serial bit patter having bit cells corresponding to at least some of the bit cells of the first serial bit pattern of the coded signal; c. generation means connected to said storing means for causing said storing means to generate the predetermined signal; d. means connected to said storing means and to said detecting means for successively comparing the respective conditions of the second serial bit pattern of the predetermined signal with the respective states of the first serial bit pattern of the coded signal; and e. means connected to said comparing means and being responsive to a predetermined relation between the states of the second serial bit pattern of the predetermined signal and the first serial bit pattern of the coded signal for producing an output signal to interrupt the operation of the apparatus.
Claim 22
Dependent Claim
167 words
The apparatus of claim 16 in which said apparatus is assigned an address, the address being representable by the information borne by an address portion of the signal including the first serial bit pattern the signal further including a command portion representing a command to Be executed by the apparatus, the command portion including another serial bit pattern having at least one command bit cell of the signal following the address bit cells, the second serial bit pattern consisting of second address bit cells, said apparatus further comprising: a. means connected to said storage means and said comparing means for enabling comparison by said comparing means only of the first and second serial bit patterns of the signal and predetermined signal, and b. means for registering a response to the signal associated with the command bit cell thereof, the registration being contingent upon the completion of comparison of the first serial bit pattern of the coded signal and the second serial bit pattern of the predetermined signal.
Claim 23
Dependent Claim
77 words
The apparatus of claim 17, in which said output signal producing means is responsive to the mismatch of condition of corresponding address bit cells of the predetermined signal and the signal to disable said comparing means before the termination of comparison of the address portions, whereby the apparatus is prevented from responding to the command bit cell in all cases in which the respective address portions of the signal and the predetermined signal do not exactly correspond.
Claim 24
Dependent Claim
74 words
The apparatus of Claim 18, further comprising: a. said registering means being responsive to register a response to the command bit cell only after receipt of a data enabling signal; b. operation bit generation means connected to said registering means and associated with said generation means for producing operation bit signal and transmitting the operation bit signal to said registering means between the address bit cells and the command bit cell of the signal.
Claim 25
Dependent Claim
90 words
The apparatus of claim 18, further comprising: a. said registering means being responsive to register a response to the condition of the data signal during the command bit cell only simultaneously with the receipt by the registering means of a second enabling signal; and b. second generation means connected to said registering means and associated with said generation means and being responsive to the receipt of the signal during the command bit cell to produce and transmit to said registering means the second enabling signal during the command bit cell.
Claim 26
Dependent Claim
50 words
The apparatus of claim 17 in which: said comparing means comprises an exclusive OR gate having a first input connected to said detecting means and a second input connected to said storing means, whereby both the signal and the predetermined signal may be compared during the address bit cells thereof.
Claim 27
Dependent Claim
48 words
The apparatus of claim 18, in which said registering means comprises: a latch circuit having a two stage output, the condition of the output being latchable in one of the states in partial response to receipt of a predetermined condition of the signal during the command bit cell.
Claim 28
Dependent Claim
104 words
The apparatus of claim 17, in which the signal is capable of assuming first and second conditions, the first and second conditions being the presence and absence, respectively of a tone burst, said detecting means of said apparatus comprising: a. a tone burst detector connected to receive the signal for producing an output including first and second stages, the first stage corresponding to the first condition, the second stage corresponding to the second condition; and b. an edge detector connected to the output of said tone burst detector for generating at its output a pulse whenever the output of the tone detector changes states.
Claim 29
Dependent Claim
82 words
The apparatus of claim 23 in which said tone burst detector comprises: a retriggerable one shot circuit connected to receive the tone bursts and having an output, the time of said one shot being greater than the period of the wave of the tone bursts, whereby said tone burst detector produces a substantially rectangular waveform at the output of said retriggerable one shot substantially only during the presence of the tone bursts regardless of distortion which may exist in the tone bursts.
Claim 30
Dependent Claim
162 words
The apparatus of claim 24, the signal being encoded in a split phase mark digital binary manner in which the condition of the signal representing a logical one bit is characterized by a change of state of the tone burst between presence and absence thereof approximately in the center of its corresponding bit cell, and the condition of the signal representing a logical zero bit is characterized by the absence of a change of state of the tone burst between presence and absence thereof during its associated bit cell, said apparatus further comprising a data and clock generator means connected to said detector for generating a clock signal at the beginning of each bit cell of the signal and for producing a data signal having a first state during bit cells of the signals in which the signal represents a logical one bit and a second state during bit cells of the signals in which the signals represent a logical zero bit.
Claim 31
Dependent Claim
185 words
The apparatus of claim 17, further comprising: a. data and clock generator means connected to said detecting means for generating a clock pulse at the beginning of each bit cell of the signal, and for generating a data signal having a state dependent upon the condition of the signal during the bit cell of the signal during which the data signal is generated; b. said generation means comprising a counter connected to receive the clock signal, said counter having an output which output has a succession of condition, the condition being dependent on the position of the counter in its count sequence, said counter being responsive to each clock signal pulse to advance one position in its count sequence; and c. said storing means comprises a read only memory having an output and having an input connected to the output of said counter, said read only memory being preprogrammed to generate at its output a predetermined sequence of output profiles, the location of said profile in the sequence at a given time being a function of the position of said counter in its count sequence.
Claim 32
Dependent Claim
92 words
The apparatus of claim 25, in which said data and clock generator means comprises: a nonretriggerable one shot circuit connected to said detecting means, the time of said one shot being greater than one half the duration of the bit cells of the signals, whereby said nonretriggerable one shot circuit is induced by the signal to emit a pulse at the beginning of each bit cell of the signal but is not affected by any changes of state of the signal occurring near the midpoint of any bit cell of the signal.
Claim 33
Dependent Claim
54 words
The apparatus of claim 17, further comprising: a data presence detector being responsive to the absence of receipt of the signal by said detecting means to reset each of said generation, storing, and comparing means to their respective states prior to reception of the signal, whereby the apparatus is prepared to analyze another signal.
Claim 34
Independent Claim
110 words
A method for decoding a coded signal having a first serial bit pattern forming one of a plurality of predetermined addresses said one address corresponding to a particular apparatus said method comprising the steps of: a. providing a second serial bit pattern corresponding to the first serial bit pattern of the one address in response to the first serial bit pattern; b. serially comparing the second serial bit pattern to the first serial bit pattern to determine matching therebetween; and c. producing a control signal in response to the determination of matching by the comparing step whereby a control signal is delivered only upon the occurrence of the one address.
Claim 35
Independent Claim
110 words
A method for decoding a coded signal having a first serial bit pattern forming one of a plurality of predetermined addresses said one address corresponding to a particular apparatus said method comprising the steps of: a. providing a second serial bit pattern corresponding to the first serial bit pattern of the one address in response to the first serial bit pattern; b. serially comparing the second serial bit pattern to the first serial bit pattern to determine matching therebetween; and c. producing a control signal in response to the determination of matching by the comparing step whereby a control signal is delivered only upon the occurrence of the one address.
Claim 36
Dependent Claim
74 words
A method in accordance with claim 29 and further comprising the steps of: a. providing a terminating signal in response to the absence of matching between the first and second serial bit patterns; and b. interrupting the decoding in response to the occurrence of the terminating signal, whereby the decoding of a coded signal hAving a first serial bit pattern which does not form the one address is not permitted to proceed to completion.
Claim 37
Dependent Claim
36 words
A method in accordance with claim 30 and further comprising the step of reactivating the operation to decode a subsequent coded signal in response to the termination of the end of a first serial bit pattern.
Claim 38
Dependent Claim
52 words
A method in accordance with claim 29 in which the step of providing a second serial bit pattern is also executed in response to a special predetermined address serial bit pattern different from the one address, said comparing step determining correspondence upon the occurrence of the special predetermined address serial bit pattern.
Claim 39
Independent Claim
141 words
A method for decoding a coded signal having a first serial bit pattern representing one of a plurality of address signals for an apparatus and another serial bit pattern representing a command signal said method comprising the steps of: a. providing a second serial bit pattern corresponding to the first serial bit pattern of the one address in response only to the occurrence of the first serial bit pattern; b. serially comparing the bits of the second serial bit pattern to those of the first serial bit pattern to determined matching therebetween; c. producing an enabling signal in response to the determination of matching in said comparing step; d. decoding the another serial bit pattern of the command signal in response to the occurrence of the enabling signal; and e. providing a control signal in response to the decoded command signal.
Claim 40
Independent Claim
141 words
A method for decoding a coded signal having a first serial bit pattern representing one of a plurality of address signals for an apparatus and another serial bit pattern representing a command signal said method comprising the steps of: a. providing a second serial bit pattern corresponding to the first serial bit pattern of the one address in response only to the occurrence of the first serial bit pattern; b. serially comparing the bits of the second serial bit pattern to those of the first serial bit pattern to determined matching therebetween; c. producing an enabling signal in response to the determination of matching in said comparing step; d. decoding the another serial bit pattern of the command signal in response to the occurrence of the enabling signal; and e. providing a control signal in response to the decoded command signal.
Claim 41
Dependent Claim
78 words
A method for decoding a coded signal in accordance with claim 33 and further comprising the steps of: a. providing a terminating signal in response to the absence of matching between the second serial bit pattern and the first serial bit pattern; and b. interrupting the decoding in response to the occurrence of the terminating signal, whereby the decoding of a coded signal having a first serial bit pattern which does not form the one address is interrupted.
Claim 42
Dependent Claim
38 words
A method in accordance with claim 34 and further comprising the step of reactivating the decoding of a subsequent serial bit pattern in response to the termination of the end of an address signal following the terminating signal.
Claim 43
Dependent Claim
68 words
A method in accordance with claim 33 in which the step of providing a second serial bit pattern corresponding to the first serial bit pattern of the one address in response to occurrence of the first serial bit pattern is also responsive to a special predetermined address different from any of the plurality of addresses, said comparing step determining matching upon the occurrence of the special predetermined address.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-09-09 | 1978-03-11 | 1978-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-09 | 1982-03-11 | 1982-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-09-09 | 1986-03-11 | 1986-09-10 | $7700.00 | Window Closed / Lapsed |