Digital delta encoder and decoder

Claim 1

Delta or incremental encoding apparatus comprising: a. a source of an incoming amplitude-varying first signal; b. clock pulse source means; c. clocked comparator means connected to receive the incoming amplitude-varying first signal, to receive a comparison second signal representative of the amplitude of the incoming signal at the time of the occurrence of the last preceding clock pulse, to receive clock pulses from the clock pulse source means and to produce a comparator output signal having a first parameter having significance of logical 1 when the amplitude of the said first signal is greater than that of the second signal and having a second parameter having significance of logical 0 when the amplitude of the said first signal is less than that of the second signal; d. pulse sequence means connected to receive the comparator output signals and, responsively thereto, to produce a third signal responsively to a sequence of a predetermined number of comparator output signals of like significance and to produce a fourth signal responsively to a sequence of a predetermined number of comparator output signals of alternately unlike significance; e. companding counter means connected to receive the said third signal and responsively thereto to increase its count and to receive the said fourth signal and responsively thereto to decrease its count; f. companding counter overflow prevention means connected to inhibit the effect of the said third signal when the companding counter means contains its maximum count and to inhibit the effect of the said fourth signal when the companding counter means contains its minimum count; g. register means h. adder means connected to receive the comparator output signals and, responsively to the first parameter thereof to add, and responsively to the second parameter thereof to subtract, the content of the companding counter means to and from the content of register means; i. register overflow prevention means connected to inhibit the operation of the adder means responsively to the first parameter of the comparator output signal when the content of the register means is less than the maximum content of the register means by less than the maximum count of the companding counter means and to inhibit the operation of the adder means responsively to the second parameter of the comparator output signal when the content of the register means is greater than zero by less than the maximum count of the companding counter means; j. digital to analogue converter means connected to the register means to produce an analogue signal representative of its contents as the said comparison second signal and apply the same to the clocked comparator means; k. encoder output terminal means connected to the comparator means to receive the said comparator output signals.