Keyed agc circuit

Claim 2

In an automatic gain control circuit of the type which is responsive to synchronizing signal components of a composite video signal, said synchronizing signal components comprising pulses of different time duration, the combination comprising: a source of recurrent pulses normally in time coincidence with said synchronizing signal pulses, said recurrent pulses having a longer time duration than the shortest duration ones of said synchronizing signal pulses; means for supplying said composite video signal including said synchronizing signal pulses; amplitude sensitive circuit means responsive to said video signals for maintaining a first conductive condition for video signals of a first polarity with respect to a threshold level and for translating video signal excursions of opposite polarity with respect to said threshold level; a peak detector circuit coupled to said amplitude sensitive circuit means for detecting said translated video signal excursions, said peak detector exhibiting a time constant suitable for peak detection of each of said synchronizing signal pulses of different duraTion; keying means coupled to said source of recurrent pulses and to said peak detector circuit for providing, during the occurrence of said recurrent pulses, a variable current determined by the amplitude of the detected signal developed by said peak detector circuit; and output filter circuit means, coupled to said keying means for developing an automatic gain control voltage determined by said variable current developed by said keying means.

Claim 3

An automatic gain control circuit as described in claim 1, wherein the charging and discharging time constant for said peak detector circuit is less than the width of said recurrent synchronizing signal components.

Claim 4

An automatic gain control circuit as described in claim 2, including: discharging means coupled between said peak detector circuit and said output filter circuit means for discharging said detected signal developed across said peak detector circuit when said recurrent pulses are not present.

Claim 5

An automatic gain control circuit of the type described in claim 3, wherein: said keying means comprises current draining means coupled to said output filter circuit means for discharging said output filter circuit means, the draining current being dependent upon the detected signal developed across said peak detector circuit.

Claim 6

An automatic gain control circuit of the type described in claim 4, including: a noise protection circuit responsive to impulse noise accompanying said video signal for providing a discharge path for said detected signal developed across said peak detector circuit in the presence of said impulse noise.

Claim 7

An automatic gain control circuit of the type described in claim 5, wherein: said noise protection circuit comprises a unidirectional current conducting device coupled between said peak detector circuit and said output filter circuit such that in the presence of said impulse noise and when said recurrent voltage pulse is not present, charging current is supplied to said output filter circuit means.

Claim 8

An automatic gain control circuit of the type described in claim 6, wherein said keying means includes a current source responsive to the amplitude of the detected signal developed across said peak detector circuit.

Claim 9

An automatic gain control circuit as described in claim 7, wherein said current source includes first, second, and third transistors, each having base, collector, and emitter electrodes, with the base of said first transistor coupled to the emitter of the second transistor and the base of the second transistor coupled to said peak detector circuit; the base of said third transistor being coupled to said source of recurrent pulses and to the emitter of said first transistor, emitter current of said first transistor in the presence of said recurrent pulses being determined by the voltage detected by said peak detector circiut.

Claim 10

An automatic gain control circuit as described in claim 8, wherein said current draining means includes a fourth transistor having base, collector and emitter electrodes wherein the collector of said fourth transistor is coupled to said output filter circuit; and the base of said fourth transistor is coupled to the collector of said first transistor such that collector current in said fourth transistor is determined by emitter current of said first transistor.

Claim 11

An automatic gain control circuit as described in claim 9 wherein said first and second transistors are of one type conductivity while said third and fourth transistors are of opposite type conductivity.

Claim 12

An automatic gain control circuit of the type described in claim 10 wherein said noise protection circuit includes: fifth, sixth, and seventh transistors, each having base, collector and emitter electrodes; a first filtering circuit for filtering said impulse noise and coupled to the base of said fifth transistor; a first clamping circuit coupled between the emitter of said fifth transistor and the base oF said sixth transistor for providing a clamping voltage to the base of said sixth transistor; said sixth transistor biased such that in the presence of said clamping voltage, said sixth transistor is turned on; a first resistive device coupled between the base of said seventh transistor and the emitter of said sixth transistor; the collector of said seventh transistor coupled through a second resistive device to said peak detector circuit; said seventh transistor operative such that when said sixth transistor is turned on, said seventh transistor provides a discharge path for the detected signal developed across said peak detector circuit.

Claim 13

A keyed automatic gain control circuit comprising: first, second, third, fourth and fifth transistors each having base, emitter and collector electrodes; means providing a source of video signals having recurrent synchronizing pulse components coupled to the base electrode of said first transistor, said synchronizing pulse components extending in a first polarity direction; means providing a source of recurrent keying pulses normally in time coincidence with said recurrent synchronizing pulse components coupled to the base electrode of said second transistor, said keying pulses extending in a polarity direction opposite to that of said first polarity direction; output circuit means for developing an automatic gain control voltage coupled to the emitter of said second transistor; a capacitance device coupled between a point of reference potential and the base of said third transistor; a first unidirectional current conducting device coupled between the collector of said first transistor and the base of said third transistor; said first unidirectional current conducting device and said capacitance device forming a peak detector for detecting voltage excursions at the collector of said first transistor; a second unidirectional current conducting device coupled between said first unidirectional current conducting device and the emitter of said second transistor; the base of said fourth transistor coupled to the emitter of said third transistor and the collector of said fourth transistor coupled to the base of said fifth transistor; the emitter of said fourth transistor coupled to the base of said second transistor; and a third unidirectional current conducting device coupled between the base of said fifth transistor and said point of reference potential; the collector of said fifth transistor coupled to said output circuit means and the emitter of said fifth transistor coupled to said point of reference potential.

Claim 14

A keyed automatic gain control circuit comprising: first, second, third, fourth and fifth transistors each having base, emitter and collector electrodes; means providing a source of video signals having recurrent synchronizing pulse components coupled to the base electrode of said first transistor, said synchronizing pulse components extending in a first polarity direction; means providing a source of recurrent keying pulses normally in time coincidence with said recurrent synchronizing pulse components coupled to the base electrode of said second transistor, said keying pulses extending in a polarity direction opposite to that of said first polarity direction; output circuit means for developing an automatic gain control voltage coupled to the emitter of said second transistor; a capacitance device coupled between a point of reference potential and the base of said third transistor; a first unidirectional current conducting device coupled between the collector of said first transistor and the base of said third transistor; said first unidirectional current conducting device and said capacitance device forming a peak detector for detecting voltage excursions at the collector of said first transistor; a second unidirectional current conducting device coupled between said first unidirectional current conducting device and the emitter of said second transistor; the base of said fourth transistor coupled to the emitter of said third transistor and the collector of said fourth transistor coupled to the base of said fifth transistor; the emitter of said fourth transistor coupled to the base of said second transistor; and a third unidirectional current conducting device coupled between the base of said fifth transistor and said point of reference potential; the collector of said fifth transistor coupled to said output circuit means and the emitter of said fifth transistor coupled to said point of reference potential.

Claim 15

A keyed automatic gain control circuit as described in claim 12 wherein the charging and discharging time constant for said capacitance device is less than the width of said recurrent synchronizing pulse components.

Claim 16

A keyed automatic gain control circuit as described in claim 13, including: means responsive to impulse noise accompanying said video signal coupled between said means for providing a source of video signals and said capacitance device to provide a discharging path for said capacitance device in the presence of said impulse noise.

Claim 17

An automatic gain control circuit as described in claim 14 including means for biasing said first transistor such that when voltage excursions of said synchronizing pulse components extend in said first polarity direction beyond a chosen threshold voltage, said first transistor operates to provide a voltage at its collector representative of the amplitude of the voltage excursions of said recurrent synchronizing pulse components, said collector voltage being peak detected by said capacitance device and said first unidirectional current conducting device; said capacitance device discharging through said second unidirectional current conducting device when said keying pulse is not present.

Claim 18

A keyed automatic gain control circuit as described in claim 15 wherein the peak deteCted voltage across said capacitance device operates to control the current flowing in the collector of said fifth transistor.

Claim 19

A keyed automatic gain control circuit as described in claim 16 wherein said means responsive to said impulse noise includes: sixth, seventh, and eighth transistors, each having base, collector and emitter electrodes; a first filtering circuit for passing said impulse noise coupled to the base of said sixth transistor; a first clamping circuit coupled between the emitter of said sixth transistor and the base of said seventh transistor for providing a clamping voltage to the base of said seventh transistor; said seventh transistor biased such that in the presence of said clamping voltage, said seventh transistor is turned on; a first resistive device coupled between the base of said eighth transistor and the emitter of said seventh transistor; the collector of said eighth transistor coupled through a second resistive device to said capacitance device; said eighth transistor operative such that when said seventh transistor is turned on, said eighth transistor provides a discharge path for charge on said capacitance device.

Claim 20

A keyed automatic gain control circuit as described in claim 17 wherein said first, second, fifth, sixth, seventh and eighth transistors are of the NPN type and said third and fourth transistors are of the PNP type.

Claim 21

A keyed automatic gain control device as described in claim 17 wherein said means for providing a source of recurrent keying pulses includes: a third resistive device coupled to the base of the second transistor; and a fourth unidirectional current conducting device coupled between a point of reference potential and said third resistive element; said recurrent keying pulses being coupled to the common terminal formed by said fourth unidirectional current conducting device and said third resistive device.