US3833902A
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US
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Integrating a-d conversion system
Assignee: Individual
•
Filing: 1972-10-05
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Granted: 1974-09-03
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Expires: 1992-10-05
Abstract
Abstract An integrating A-D conversion system which is adapted to provide an analog input voltage in the form of a binary number and comprises the steps of (1) positively integrating a positive analog input voltage for a period of time 2T, (2) subtracting from the resulting voltage in (1) a negative voltage produced by integrating a negative reference voltage -Vr for a period of time T, (3) adding the resulting voltage in (2) with a negative (or positive) voltage produced by integrating the voltage -Vr (or +Vr) for a period of time T/2 according as the resulting voltage in (2) is positive (or negative), (4) adding the resulting voltage in (3) with a negative (or positive) voltage produced by integrating the voltage -Vr (or +Vr) for a period of time T/4 according as the resulting voltage in (3) is positive (or negative), (5) adding the resulting voltage in (4) with a negative (or positive) voltage produced by integrating the voltage -Vr (or +Vr) for a period of time T/8 according as the resulting voltage in (4) is positive (or negative), (6) adding the resulting voltage in (5) with a negative (or positive) voltage produced by integrating the voltage -Vr (or +Vr) for a period of time T/16 according as the resulting voltage in (5) is positive (or negative), . . . . and so on, and obtaining a digital output, representing a binary number whose digits are determined by whether the corresponding resulting voltages in (2), (3), . . . . are positive or negative respectively.
Inventors
- 👤 T Eto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:42
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/50; H03M1/52; H03M1/14; H03M1/16
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
395 words
An integrating A-D conversion method for converting an analog input voltage into a digital output in the form of a binary number having n digits consisting of first, second, third . . . (n -1)th and nth digits, which comprises the sequential steps A0, A1, A2, A3, . . . A(n-1), An and B; A0: integrating a positive (or negative) analog input voltage by integrating means for a predetermined period of time; A1: integrating a negative (or positive) reference voltage by the integrating means for a period of time T and storing a digital signal ''''1'''' (or ''''0) in a first storage means when an output derived from the integrating means at the end of the step A1 is positive (or negative); A2: integrating the negative (or positive) reference voltage by the integrating means for a period of time 2T/(22) and storing a digital signal ''''1'''' (or ''''0'''') in a second storage means when an output derived from the integrating means at the end of the step A2 is positive (or negative); A3: integrating the negative (or positive) reference voltage by the integrating means for a period of time 2T/(23) and storing a digital signal ''''1'''' (or ''''0'''') in a third storage means when an output derived from the integrating means at the end of the step A3 is positive (or negative); . . . . . . . . A -1: integrating the negative (or positive) reference voltage by the integrating means for a period of time 2T/(2)n-1 and storing a digital signal ''''1'''' (or ''''0'''') in an (n -1)th storage means when an output derived from the integrating means at the end of the step An-1 is positive (or negative); An: integrating the negative (or positive) reference voltage by the integrating means for a period of time 2T/(2)n and storing a digital signal ''''1'''' (or ''''0'''') in a nth storage means when an output derived from the first integrating means at the end of the step An is positive (or negative); B: applying the digital signals stored in the first, second, third, . . . (n-1)th and nth storage means to an output storage circuit to store them therein; thereby providing a digital output in the form of a binary number having n digits consisting of the first, second, third, (n-1)th, and nth digits in order of significance stored in the storage circuit.
Claim 2
Dependent Claim
395 words
An integrating A-D conversion method for converting an analog input voltage into a digital output in the form of a binary number having n digits consisting of first, second, third . . . (n -1)th and nth digits, which comprises the sequential steps A0, A1, A2, A3, . . . A(n-1), An and B; A0: integrating a positive (or negative) analog input voltage by integrating means for a predetermined period of time; A1: integrating a negative (or positive) reference voltage by the integrating means for a period of time T and storing a digital signal ''''1'''' (or ''''0) in a first storage means when an output derived from the integrating means at the end of the step A1 is positive (or negative); A2: integrating the negative (or positive) reference voltage by the integrating means for a period of time 2T/(22) and storing a digital signal ''''1'''' (or ''''0'''') in a second storage means when an output derived from the integrating means at the end of the step A2 is positive (or negative); A3: integrating the negative (or positive) reference voltage by the integrating means for a period of time 2T/(23) and storing a digital signal ''''1'''' (or ''''0'''') in a third storage means when an output derived from the integrating means at the end of the step A3 is positive (or negative); . . . . . . . . A -1: integrating the negative (or positive) reference voltage by the integrating means for a period of time 2T/(2)n-1 and storing a digital signal ''''1'''' (or ''''0'''') in an (n -1)th storage means when an output derived from the integrating means at the end of the step An-1 is positive (or negative); An: integrating the negative (or positive) reference voltage by the integrating means for a period of time 2T/(2)n and storing a digital signal ''''1'''' (or ''''0'''') in a nth storage means when an output derived from the first integrating means at the end of the step An is positive (or negative); B: applying the digital signals stored in the first, second, third, . . . (n-1)th and nth storage means to an output storage circuit to store them therein; thereby providing a digital output in the form of a binary number having n digits consisting of the first, second, third, (n-1)th, and nth digits in order of significance stored in the storage circuit.
Claim 3
Dependent Claim
60 words
A method of converting an analog input voltage into a digital output according to claim 1, in which the change of charge during each step is determined by integrating a fixed magnitude reference voltage of polarity inverse to the charge remaining after the preceding step for a time interval that is one half the time interval of the preceding step.
Claim 4
Dependent Claim
63 words
A method of converting an analog input voltage into a digital output according to claim 1, in which the change of charge during each step is determined by integrating for a fixed time a fixed magnitude reference voltage of polarity inverse to the charge remaining after the preceding step through an integrator resistor the resistance of which is doubled for each succeeding step.
References Cited (Backward Citations)
US3251052A
Cited
US3449741A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-09-02 | 1978-03-04 | 1978-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-02 | 1982-03-04 | 1982-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-09-02 | 1986-03-04 | 1986-09-03 | $7700.00 | Window Closed / Lapsed |