Abstract There is disclosed a data handling system including input-output means, intermediate memory means and principal memory means, together with data transfer and processing control logic. Input and output parallel to serial and serial to parallel and code conversion capability are provided. Input-output temporary storage capability is provided by a shift register. The intermediate memory is a random access memory or the like having a storage capacity substantially exceeding that of the inputoutput shift register. The principal memory is a magnetic tape system, preferably employing a magnetic tape cassette as a memory medium. The system is useable in various ways, for example as a data terminal capable of local keyboard and/or remotely controlled data storage and transmission. Data input and output may be in parallel or serial form and a variety of data rates and data code word may be acoommodated without system modification. Broadly stated, for operation in the record mode, the system accumulates a block of data provided by a data source (for example a line of print) in the intermediate memory through the input-output means, and thereafter transfers the entire data block to the principal memory at a high speed. For playback, an entire block of data is transferred at high speed from the principal memory into the intermediate memory and is thereafter provided through the input-output means to suitable data utilization devices at a data rate compatible with such devices. Among the features provided by the system are error checking and correction on a character-by-character and data block basis, data block identification (search) based on selectable identifying code characteristics and compatibility with a variety of keyboard controlled devices or other data input and output devices, and automatic and manual data gathering and processing machinery.
A data synchronization system for handling seriAl data from a source at a predetermined nominal data rate in a form of multibit character code words comprising: means for generating a timing pulse train at a frequency which is a high multiple of said nominal data rate; means for sensing the arrival of the first bit of a character code word; means responsive to said timing pulse train and the arrival of said first bit to generate a second pulse train at said nominal frequency with the first pulse of said second pulse train in predetermined time relation to said first incoming bit; data handling circuitry coupled to said data source; and means for actuating said data handling circuitry in response to said second pulse train.
Claim 2
Dependent Claim
125 words
A data synchronization system for handling seriAl data from a source at a predetermined nominal data rate in a form of multibit character code words comprising: means for generating a timing pulse train at a frequency which is a high multiple of said nominal data rate; means for sensing the arrival of the first bit of a character code word; means responsive to said timing pulse train and the arrival of said first bit to generate a second pulse train at said nominal frequency with the first pulse of said second pulse train in predetermined time relation to said first incoming bit; data handling circuitry coupled to said data source; and means for actuating said data handling circuitry in response to said second pulse train.
Claim 3
Dependent Claim
138 words
A system as defined in claim 1 wherein said means for generating said second pulse train comprises a counter responsive to arrival of said first bit and operative thereupon to advance in response to the pulses of said first pulse train, said counter including means to provide a first output pulse at a predetermined count corresponding to the nominal center of the bit period of the first data bit of the incoming character code word to be processed by said data handling circuit; means for providing further counter output pulses at a succession of counts corresponding to the nominal centers of the bit periods for the other bits of said incoming character code word to be processed by said data handling circuit; and means for deactivating and resetting said counter when a predetermined maximum count has been reached.
Claim 4
Dependent Claim
24 words
A system as defined in claim 2 wherein the frequency of said timing pulse train is at least four times the nominal bit rate.
Claim 5
Dependent Claim
24 words
A system as defined in claim 2 wherein the frequency of said timing pulse train is at least eight times the nominal bit rate.
Claim 6
Dependent Claim
37 words
A system as defined in claim 2 wherein each character code word commences with at least one predetermined non-information bearing bit; and wherein said sensing means is responsive to said non-information bearing bit to activate said counter.
Claim 7
Dependent Claim
54 words
A system as defined in claim 5 wherein said predetermined maximum count is sufficient that the number of pulses in said second pulse train activates said data handling means a total number of times for each character code word at least equal to the number of information bearing bits in each character code word.