← Back to Patent Explorer
US3833838A Expired / Lapsed US ⏱️ 0.0 years remaining

Electronic component mounting wafers for repeated connection in a variety of circuit designs

Assignee: Individual
•
Filing: 1972-11-13
•
Granted: 1974-09-03
•
Expires: 1992-11-13
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract There is disclosed a plurality of wafers, each having a multiplicity of sets of electrically conducting pads, the pads within one set being electrically connected together and electrically isolated from each of the other sets. At least one pad in each of the sets has a connecting area adapted to receive and be soldered and unsoldered repeatedly to a conductive mounting lead of an electronic component. At least another pad in each of the sets having a connecting area adapted to receive and be soldered and unsoldered repeatedly to a conductive interconnecting lead which may connect one set of conducting pads with another. Each of the sets of pads has a thickness and shape which provides an electrically conducting path of sufficient length between each pad connecting area in the set to substantially isolate from one connecting area excessive and damaging heat from soldering and unsoldering conductive leads at another connecting area.

Inventors

  • 👤 A Christiansen

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 09:10
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/16; H05K1/02; H05K1/0286; H05K1/14; H05K1/141; H05K1/142; H05K1/162; H05K1/165; H05K1/167; H05K2201/00; H05K2201/04; H05K2201/049; H05K2201/09; H05K2201/09209; H05K2201/09372; H05K2201/09418; H05K2201/09818; H05K2201/09972; H05K2201/10; H05K2201/10227; H05K2201/10287; H05K2201/10613; H05K2201/10621; H05K2201/10689; H05K3/00; H05K3/0058; H05K3/0061; H05K3/0064; H05K3/30; H05K3/303; H05K3/305; H05K3/32; H05K3/34; H05K3/341; H05K3/3421; H05K3/36; H05K3/38; H05K3/386; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49139; Y10T29/4914; Y10T29/49142; Y10T29/49155

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 132 words
Apparatus for changeably interconnecting a multiplicity of electronic components in a plurality of different circuit configurations comprising: a wafer having a multiplicity of electrically conducting areas, each area having a non-conducting slot therein to form connecting pads which are separated and divided apart to receive and be soldered and unsoldered repeatedly to a conductive interconnecting lead, each of said conducting areas having at least one other connecting pad adapted to receive and be soldered and unsoldered repeatedly to a conductive mounting lead of an electronic component, each of said conducting areas having a shape and thickness which provides an electrically conducting path between each connecting pad of sufficient length and small cross-sectional area to substantially isolate from one connecting pad excessive and damaging heat from soldering and unsoldering at another connecting pad.
Claim 2
Dependent Claim 132 words
Apparatus for changeably interconnecting a multiplicity of electronic components in a plurality of different circuit configurations comprising: a wafer having a multiplicity of electrically conducting areas, each area having a non-conducting slot therein to form connecting pads which are separated and divided apart to receive and be soldered and unsoldered repeatedly to a conductive interconnecting lead, each of said conducting areas having at least one other connecting pad adapted to receive and be soldered and unsoldered repeatedly to a conductive mounting lead of an electronic component, each of said conducting areas having a shape and thickness which provides an electrically conducting path between each connecting pad of sufficient length and small cross-sectional area to substantially isolate from one connecting pad excessive and damaging heat from soldering and unsoldering at another connecting pad.
Claim 3
Dependent Claim 104 words
The apparatus described in claim 1 further including a plurality of said wafers and a base member having a surface thereon to which said plurality of said wafers are removeably attached and supported, said wafers being electrically interconnected in a predetermined configuration to form one of a plurality of different electronic circuit configurations, said base member having a ground plane of electrically conductive material attached to said surface to form a convenient low impedance circuit ground, said plurality of said wafers having a substantial thickness to minimize the capacitance between said conducting areas on said wafers and said ground plane of said base member.
Claim 4
Dependent Claim 215 words
The apparatus described in claim 2 wherein at least one of said plurality of said wafers comprises: a substantially flat non-conducting substrate upon one surface of which said conducting areas are fixedly secured in the form of a multiplicity of substantially pie-shaped areas, each area being a thin sheet of electrically conducting material which is electrically isolated from the other areas, the apex region of each of said substantially pie-shaped areas being a connecting pad area particularly suited to be soldered and unsoldered repeatedly to wire conductors of an electronic component, each of said substantially pie-shaped areas having said non-conductive slot located along a line extending from the edge of the base thereof to the interior of the area whereby the base region is divided into two pad connecting areas to eAch of which a conductive lead may be soldered and unsoldered repeatedly without adversely affecting a soldered connection at the other, said pie-shaped area being constructed to have a large ratio of surface area to cross section area and a substantial distance between the apex and base regions to dissipate heat and prevent damage to the electronic components fastened to the apex pad, whereby said wafer and its electronic component repeatedly can be soldered to and unsoldered from a multiplicity of different circuit configurations.
Claim 5
Dependent Claim 74 words
The apparatus described in claim 3 further including a circuit region centered on said wafer, said apex regions of each of said substantially pie-shaped areas being uniformly located around the circumference of said circular region and further including one apex region of a selected substantially pie-shaped area having a tab of conductive material extending into said circular region to provide an index marker and capacitive isolation between the areas immediately adjacent said selected area.
Claim 6
Dependent Claim 101 words
The apparatus described in claim 2 wherein at least one of said plurality of said wafers comprises a substantially flat non-conducting substrate and wherein said conducting areas comprise a pair of parallel rectangular areas of thin conducting material joined together at the midpoint of the nearest parallel edges of a third rectangular region of thin conducting material, said non-conducting slot being located between said nearest parallel edges and the edges of said third rectangular region the most distant end regions of each of said parallel rectangular areas forming connecting pad areas to which conducting leads may be repeatedly soldered and unsoldered.
Claim 7
Dependent Claim 109 words
The apparatus described in claim 2 wherein at least one of said plurality of said wafers comprises a substantially flat non-conducting substrate and wherein said conducting areas comprise a plurality of four rectangular connecting pads of thin conductive material joined by a fifth area of rectangular conductive material which overlaps a corner of each of the other four rectangular pads, said non-conducting slot being located between each pair of adjacent edges of two adjacent pads of said four rectangular connecting pads and the intersecting edge of said fifth area, said four rectangular connecting pads being particularly suited to the repeated soldering and unsoldering of conductive wires and component leads.
Claim 8
Dependent Claim 127 words
The apparatus described in claim 1 wherein at least one of said plurality of wafers comprises a substantially flat non-conducting substrate and wherein said conducting areas are thin sheets of electrically conducting material fixedly secured to one surface of said substrate adjacent two perpendicular straight lines passing through the center of said substrate to form four electrically isolated conductive sets of pads, the portions of said sets most centrally located on said substrate forming pads with connecting areas particularly suited to be fastened to a terminal of an electronic component, the regions of said sets adjacent the outer edges of said substrate forming pads with connecting areas separated by said non-conducting slots which areas are particularly suited to be soldered and unsoldered repeatedly to conductive interconnecting leads.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-09-02 1978-03-04 1978-09-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-09-02 1982-03-04 1982-09-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-09-02 1986-03-04 1986-09-03 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag