Data communication system

Claim 2

In a data communication system employing at least two transceiver units, each capable of operating in either send or receive modes with respect to the other, each of said transceivers including a document scanner and a transceiver control circuit, the combination in each of said transceivers comprising: means for selectively providing either a send or receive mode indication signal, a mode control for placing the control circuit in a first condition in response to a send mode indication signal applied to said mode control and in a second condition in response to a receive mode indication signal applied to said mode control, said circuit in said first condition responsive to an input signal received from a remote receiving transceiver unit for producing an indication that said input signal falls within a predetermined range, means responsive to said indication to enable the sending transmission, said circuit in said second condition responsive to a phasing signal received from a remote sending unit for detecting as part of said phasing signal first or second scanning speed information, and activation means responsive to said speed information for activating a corresponding speed control unit to control the speed of the document scanner.

Claim 3

The combination of claim 1 wherein said control circuit includes a detector having applied thereto a first reference potential and a second reference potential determining said predetermined range, means applying a third potential to said control circuit representative of the signal transmitted by a remote transceiver unit, said control circuit providing a first output signal where said third potential falls above the range of said first and second potential, a second output signal where said third potential lies betweEn the range of said first and second potential, and a third output signal where said third potential is below the range of said first and second potential, and a selective discrimination circuit including said mode control and responsive to the output of said detector and to said send and receive mode indication signals for providing first and second speed information signals.

Claim 4

The combination of claim 2 wherein said control circuit includes a filter responsive to said third potential, and said detector includes a resistor divider having said first and second reference potentials applied thereacross, and having a first tap coupled to a first differential amplifier input, a second tap coupled to a second differential amplifier input, and said third reference potential coupled from said filter to a junction common to the remaining differential inputs of said first and second differential amplifier units, means connecting the output of said differential amplifier to a gating means, said gating means responsive to said second output signal for providing a signal to said selective discrimination circuit, and to said third output signal for providing a signal to said activation means.

Claim 5

The combination of claim 3 wherein said selective discrimination circuit includes a first time delay circuit of a first duration operative in response to said first condition, and a second time delay circuit of a second duration operative in response to said second condition, said first duration exceeding said second duration, said first duration extending for a time longer than an average spurious input and sufficient to provide an output in response to an input signal representative of information.

Claim 6

The combination of claim 3 wherein said filter is a three pole Paynter filter having fast time domain response.

Claim 7

The combination of claim 3 wherein said enabling means includes an input terminal responsive to said third output signal, a time delay circuit activated in response to said third output signal, said activation means producing an activation signal upon the termination of said time delay for activating a speed control unit.

Claim 8

In a data communication system employing at least two transceiver units, each capable of operating in either send or receive modes with respect to the other, each of said transceivers including a document scanner and a transceiver control circuit, the combination in each of said transceivers comprising: means for selectively providing either a send or receive mode indication signal, a mode control for placing the control circuit in a first condition in response to a send mode indication signal applied to said mode control and in a second condition in response to a receive mode indication signal applied to said mode control, said circuit in said first condition responsive to an input signal received from a remote receiving transceiver unit for producing an indication that said input signal falls within a predetermined range, means responsive to said indication to enable the sending transmission, said circuit in said second condition responsive to a phasing signal received from a remote sending unit for detecting as part of said phasing signal first or second scanning speed information, and activation means responsive to said speed information for activating a corresponding speed control unit to control the speed of the document scanner, said activation means including a first counter responsive to said second condition for initiating a fixed duration counting period, detecting means responsive to an initial portion of said input signal for providing first and second signals corresponding to first and second scanning speed information, a second counter responsive to said first signal for initiating a count therein, a third counter responsive to said second signal for initiating a count therein, said second and third counter each having a predetermined maximum count condition, means responsive to termination of said fixed duration counting period for sampling said second and third counters, and means responsive to said second and third counter maximum count conditions for providing a signal indicative of said scanning speed.

Claim 9

In a data communication system employing at least two transceiver units, each capable of operating in either send or receive modes with respect to the other, each of said transceivers including a document scanner and a transceiver control circuit, the combination in each of said transceivers comprising: means for selectively providing either a send or receive mode indication signal, a mode control for placing the control circuit in a first condition in response to a send mode indication signal applied to said mode control and in a second condition in response to a receive mode indication signal applied to said mode control, said circuit in said first condition responsive to an input signal received from a remote receiving transceiver unit for producing an indication that said input signal falls within a predetermined range, means responsive to said indication to enable the sending transmission, said circuit in said second condition responsive to a phasing signal received from a remote sending unit for detecting as part of said phasing signal first or second scanning speed information, and activation means responsive to said speed information for activating a corresponding speed control unit to control the speed of the document scanner, said activation means including a first counter responsive to said second condition for initiating a fixed duration counting period, detecting means responsive to an initial portion of said input signal for providing first and second signals corresponding to first and second scanning speed information, a second counter responsive to said first signal for initiating a count therein, a third counter responsive to said second signal for initiating a count therein, said second and third counter each having a predetermined maximum count condition, means responsive to termination of said fixed duration counting period for sampling said second and third counters, and means responsive to said second and third counter maximum count conditions for providing a signal indicative of said scanning speed.

Claim 10

The combination of claim 7 further including first gating means coupled to said second counter, second gating means coupled to said third counter, said first and second gating means each responsive to the respective second and third counter maximum count conditions for disabling the respective counter if said respective counter achieves its predetermined maximum count condition during said fixed duration counting period.

Claim 11

The combination of claim 7 wherein said control circuit includes a detector having applied thereto a first reference potential and a second reference potential determining said predetermined range, means applying a third potential to said control circuit representative of the signal transmitted by a remote transceiver unit, said control circuit providing a first output signal where said third potential falls above the range of said first and second potential, a second output signal where said third potential lies between the range of said first and second potential, and a third output signal where said third potential is below the range of said first and second potential, and a selective discrimination circuit including said mode control and responsive to the output of said detector and to said send and receive mode indication signals for providing first and second speed information signals.

Claim 12

The combination of claim 7 wherein said control circuit includes a filter responsive to said third potential, and said detector includes a resistor divider having said first and second reference potentials applied thereacross, and having a first tap coupled to a first differential amplifier input, a second tap coupled to a second differential amplifier input, and said third reference potential coupled from said filter to a junction common to the remaining differential inputs of said first and second differential amplifier units, means connecting the output of said differential amplifier to a gating means, said gating means responsive to said second output signal for providing a signal to said selective discrimination circuit, and to said third output signal for providing a signal to said activation means.

Claim 13

The combination of claim 10 wherein said selective discrimination circuit includes a first time delay circuit of a first duration operative in response to said first condition, and a second time delay circuit of a second duration operative in response to said second condition, said first duration exceeding said second duration, said first duration extending for a time longer than an average spurious input and sufficient to provide an output in response to an input signal representative of information.

Claim 14

The combination of claim 10 wherein said filter is a three pole Paynter filter having fast time domain response.

Claim 15

The combination of claim 7 wherein said second and third counters each provide a time delay in accordance with said predetermined maximum count, said time delay being sufficient to ovrcome spurious noise signals.

Claim 16

In a transceiver including a document scanner and a control circuit, the combination in said control circuit comprising means for selectively providing either a send or receive mode indication signal, a mode control for placing the control circuit in a first condition in response to a send mode indication signal applied to said mode control and in a second condition in response to a receive mode indication signal applied to said mode control, said circuit in said first condition responsive to an input signal from a remote receiver for providing a range signal when said input signal falls within a predetermined range, means responsive to said range signal to enable a sending transmission, said circuit in said second condition responsive to a phasing signal from a remote transmitter for detecting whether said phasing signal includes first or second scanning speed information, and activation means responsive to said speed information for activating a corresponding speed control unit to control the speed of said document scanner.

Claim 17

In a transceiver including a document scanner and a control circuit, the combination in said control circuit comprising means for selectively providing either a send or receive mode indication signal, a mode control for placing the control circuit in a first condition in response to a send mode indication signal applied to said mode control and in a second condition in response to a receive mode indication signal applied to said mode control, said circuit in said first condition responsive to an input signal from a remote receiver for providing a range signal when said input signal falls within a predetermined range, means responsive to said range signal to enable a sending transmission, said circuit in said second condition responsive to a phasing signal from a remote transmitter for detecting whether said phasing signal includes first or second scanning speed information, and activation means responsive to said speed information for activating a corresponding speed control unit to control the speed of said document scanner.

Claim 18

The combination of claim 14 wherein said control circuit includes a detector having applied thereto a first reference potential and a second reference potential determining said predetermined range, means applying a third potential to said control circuit representative of said input signal, said control circuit providing a first output signal where said third potential falls above the range of said first and second potential, a second output signal where said third potential lies between the range of said first and second potential, and a third output signal where said third potential is below the range of said first and second potential, and a selective discrimination circuit including said mode control and responsive to the output of said detector and to said send and receive mode indication signals for providing first and second speed information signals.

Claim 19

The combination of claim 15 wherein said control circuit includes a filter responsive to said third potential, and said detector includes a resistor divider having said first and second reference potentials applied thereacross, and having a first tap coupled to a first differential amplifier input, a second tap coupled to a second differential amplifier input, and said third reference potential coupled from said filter to a junction common to the remaining differential inputs of said first and second differential amplifier units, means connecting the output of said differential amplifier to a gating means, said gating means responsive to said second output signal for providing a signal to said selective discrimination circuit, and to said third output signal for providing a signal to said activation means.

Claim 20

The combination of claim 16 wherein said selective discrimination circuit includes a first time delay circuit of a first duration operative in response to said first condition, and a second time delay circuit of a second duration operative in response to said second condition, said first duration exceeding said second duration, said first duration extending for a time longer than an average spurious input and sufficient to provide an output in response to said input signal.

Claim 21

The combination of claim 16 wherein said filter is a three pole Paynter filter having fast time domain response.

Claim 22

The combination of claim 16 wherein said activation means includes an input terminal responsive to said third output signal, a time delay circuit activated in response to said third output signal, said activation means producing an activation signal upon the termination of said time delay for activating a speed control unit.

Claim 23

In a transceiver including a document scanner and a control circuit, the combination in said control circuit comprising means for selectively providing a send or receive mode indication signal, a mode control for placing the control circuit in a first condition in response to a send mode indication signal applied to said mode control and in a second condition in response to a receive mode indication signal applied to said mode control, said circuit in said first condition responsive to an input signal from a remote receiver for providing a range signal when said input signals falls within a predetermined range, means responsive to said range signal to enable a sending transmission, said circuit in said second condition responsive to a phasing signal from a remote transmitter for detecting whether said phasing signal includes first or second scanning speed information, and activation means responsive to said speed information for activating a corresponding speed control unit to control the speed of said document scanner, said activation means including a first counter responsive to said second condition for initiating a fixed duration counting period, detecting means responsive to an Initial portion of said input signal for providing first and second signals corresponding to first and second scanning speed information, a second counter responsive to said first signal for initiating a count therein, a third counter responsive to said second signal for initiating a count therein, said second and third counter each having a predetermined maximum count condition, means responsive to termination of said fixed duration counting period for sampling said second and third counters, and means responsive to said second and third counter maximum count conditions for providing a signal indicative of either said first or said second scanning speed.

Claim 24

In a transceiver including a document scanner and a control circuit, the combination in said control circuit comprising means for selectively providing a send or receive mode indication signal, a mode control for placing the control circuit in a first condition in response to a send mode indication signal applied to said mode control and in a second condition in response to a receive mode indication signal applied to said mode control, said circuit in said first condition responsive to an input signal from a remote receiver for providing a range signal when said input signals falls within a predetermined range, means responsive to said range signal to enable a sending transmission, said circuit in said second condition responsive to a phasing signal from a remote transmitter for detecting whether said phasing signal includes first or second scanning speed information, and activation means responsive to said speed information for activating a corresponding speed control unit to control the speed of said document scanner, said activation means including a first counter responsive to said second condition for initiating a fixed duration counting period, detecting means responsive to an Initial portion of said input signal for providing first and second signals corresponding to first and second scanning speed information, a second counter responsive to said first signal for initiating a count therein, a third counter responsive to said second signal for initiating a count therein, said second and third counter each having a predetermined maximum count condition, means responsive to termination of said fixed duration counting period for sampling said second and third counters, and means responsive to said second and third counter maximum count conditions for providing a signal indicative of either said first or said second scanning speed.

Claim 25

The combination of claim 20 further including first gating means coupled to said second counter, second gating means coupled to said third counter, said first and second gating means each responsive to the respective second and third counter maximum count conditions for disabling the respective counter if said respective counter achieves its predetermined maximum count condition during said fixed duration counting period.

Claim 26

The combination of claim 20 wherein said control circuit includes a detector having applied thereto a first reference potential and a second reference potential determining said predetermined range, means applying a third potential to said control circuit representative of said input signal, said control circuit providing a first output signal where said third potential falls above the range of said first and second potential, a second output signal where said third potential lies between the range of said first and second potential, and a third output signal where said third potential is below the range of said first and second potential, and a selective discrimination circuit including said mode control and responsive to the output of said detector and to said send and receive mode indication signals for providing said first and second scanning speed signals.

Claim 27

The combination of claim 20 wherein said control circuit includes a filter responsive to said third potential, and said detector includes a resistor divider having said first and second reference potentials applied thereacross, and having a first tap coupled to a first differential amplifier input, a second tap coupled to a second differential amplifier input, and said third reference potential coupled from said filter to a junction common to the remaining differential inputs of said first and second differential amplifier units, means connecting the output of said differential amplifier to a gating means, said gating means responsive to said second output signal for providing a signal to said selective discrimination circuit, and to said third output condition for providing a signal to said activation means.

Claim 28

The combination of claim 23 wherein said selective discrimination circuit includes a first time delay circuit of a first duration operative in response to said first condition, and a second time delay circuit of a second duration operative in response to said second condition, said first duration exceeding said second duration, said first duration extending for a time longer than an average spurious input and sufficient to provide an output in response to said input signal.

Claim 29

The combination of claim 23 wherein said filter is a three pole Paynter filter having fast time domain response.

Claim 30

The combination of claim 20 wherein said second and third counters each provide a time delay in accordance with said predetermined maximum count, said time delay being sufficient to overcome spurious noise signals.

Claim 31

A transceiver control circuit operative in either a send mode to enable transmission or a receive mode to provide a document scanner speed control signal and comprising means for selectively providing either a send or receive mode indication signal, a mode control for placing the control circuit in said send mode in response to a send mode indication signal applied to said mode control and in said receive mode in response to a receive mode indication signal applied to said mode control, said circuit in said send mode responsive to a first input signal from a remote receiver for determining the presence of a desired component therein, means responsive to the presence of said component for enabling transmission, said circuit in said receive mode responsive to a second input signal from a remote transmitter for detecting a further desired component containing scanning speed information, and providing means responsive to the detection of said further desired component for providing said document scanner speed control signal.

Claim 32

A transceiver control circuit operative in either a send mode to enable transmission or a receive mode to provide a document scanner speed control signal and comprising means for selectively providing either a send or receive mode indication signal, a mode control for placing the control circuit in said send mode in response to a send mode indication signal applied to said mode control and in said receive mode in response to a receive mode indication signal applied to said mode control, said circuit in said send mode responsive to a first input signal from a remote receiver for determining the presence of a desired component therein, means responsive to the presence of said component for enabling transmission, said circuit in said receive mode responsive to a second input signal from a remote transmitter for detecting a further desired component containing scanning speed information, and providing means responsive to the detection of said further desired component for providing said document scanner speed control signal.

Claim 33

The combination of claim 27 wherein said control circuit includes a detector having applied thereto a first reference potential and a second reference potential determining a range representing said desired component, means applying a third potential to said control circuit representative of said first input signal, said control circuit providing a first output signal where said third potential falls above said range, a second output signal where said third potential lies within said range, and a third output signal where said third potential is below said range, and a selective discrimination circuit including said mode control and responsive to the output of said detector and to said send and receive mode indication signals for providing first and second speed information signals.

Claim 34

The combination of claim 28 wherein said control circuit includes a filter responsive to said third potential, and said detector includes a resistor divider having said first and second reference potentials applied thereacross, and having a first tap coupled to a first differential amplifier input, a second tap coupled to a second differential amplifier input, and said third reference potential coupled from said filter to a junction common to the remaining differential inputs of said first and second differential amplifier units, means connecting the output of said differential amplifier to a gating means responsive to said second output signal for providing a signal to said selective discrimination circuit, and to said third output signal for providing a signal to said activation means.

Claim 35

The combination of claim 29 wherein said selective discrimination circuit includes a first time delay circuit of a first duration operative in response to said first output signal, and a second time delay circuit of a second duration operative in response to said second output signal, said first duration exceeding said second duration, said first duration extending for a time longer than an average spurious input and sufficient to provide an output in response to said input signal.

Claim 36

The combination of claim 29 wherein said filter is a three pole Paynter filter having fast time domain response.

Claim 37

The combination of claim 29 wherein said providing means includes an input terminal responsive to said third output signal, a time delay circuit activated in response to said third output signal, said providing means providing said control signal upon the termination of said time delay.

Claim 38

A transceiver control circuit operative in either a send mode to enable transmission or a receive mode to provide a control signal, and comprising means for selectively providing either a send or receive mode indication signal, a mode control for placing the control circuit in said mode in response to a send mode indication signal applied to said mode control and in said receive mode in response to a receive mode indication signal applied to said mode control, said circuit in said send mode responsive to a first input signal from a remote receiver for determining the presence of a desired component therein, means responsive to the presence of said component for enabling transmission, said circuit in said receive mode responsive to a second input signal from a remote transmitter for detecting a further desired component, and providing means responsive to the detection of said further desired comPonent for providing said control signal, said providing means including a first counter actuated when said control circuit is in said receive mode for initiating a fixed duration counting period, detecting means responsive to an initial portion of said second input signal for providing first and second signals corresponding to first and second input signal characteristics, a second counter responsive to said first signal for initiating a count therein, a third counter responsive to said second signal for initiating a count therein, said second and third counter each having a predetermined maximum count condition, means responsive to termination of said fixed duration counting period for sampling said second and third counters, and means responsive to said second and third counter maximum count conditions for providing a signal indicative of either said first or said second input signal characteristics.

Claim 39

A transceiver control circuit operative in either a send mode to enable transmission or a receive mode to provide a control signal, and comprising means for selectively providing either a send or receive mode indication signal, a mode control for placing the control circuit in said mode in response to a send mode indication signal applied to said mode control and in said receive mode in response to a receive mode indication signal applied to said mode control, said circuit in said send mode responsive to a first input signal from a remote receiver for determining the presence of a desired component therein, means responsive to the presence of said component for enabling transmission, said circuit in said receive mode responsive to a second input signal from a remote transmitter for detecting a further desired component, and providing means responsive to the detection of said further desired comPonent for providing said control signal, said providing means including a first counter actuated when said control circuit is in said receive mode for initiating a fixed duration counting period, detecting means responsive to an initial portion of said second input signal for providing first and second signals corresponding to first and second input signal characteristics, a second counter responsive to said first signal for initiating a count therein, a third counter responsive to said second signal for initiating a count therein, said second and third counter each having a predetermined maximum count condition, means responsive to termination of said fixed duration counting period for sampling said second and third counters, and means responsive to said second and third counter maximum count conditions for providing a signal indicative of either said first or said second input signal characteristics.

Claim 40

The combination of claim 33 further including first gating means coupled to said second counter, second gating means coupled to said third counter, said first and second gating means each responsive to the respective second and third counter maximum count for disabling the respective counter if said respective counter achieves its predetermined maximum count condition during said fixed duration counting period.

Claim 41

The combination of claim 33 wherein said control circuit includes a detector having applied thereto a first reference potential and a second reference potential determining a predetermined range, means applying a third potential to said control circuit representative of said input signal, said control circuit providing a first output signal where said third potential falls above the range of said first and second potential, a second output signal where said third potential lies between the range of said first and second potential, and a third output signal where said third potential is below the range of said first and second potential, and a selective discrimination circuit including said mode control and responsive to the output of said detector and to said send and receive mode indication signals for providing said first and second characteristic signals.

Claim 42

The combination of claim 33 wherein said control circuit includes a filter responsive to said third potential and said detector includes a resistor divider having said first and second reference potentials applied thereacross, and having a first tap coupled to a first differential amplifier input, a second tap coupled to a second differential amplifier input, and said third reference potential coupled from said filter to a junction common to the remaining differential inputs of said first and second differential amplifier units, means connecting the output of said differential amplifier to a gating means, said gating means responsive to said second output signal for providing a signal to said selective discrimination circuit, and to third output signal for providing a signal to said providing means.

Claim 43

The combination of claim 36 wherein said selective discrimination circuit includes a first time delay circuit of a first duration operative in response to said first output signal, and a second time delay circuit of a second duration operative in response to said second output signal, said first duration exceeding said second duration, said first duration extending for a time longer than an average spurious input and sufficient to provide an output in response to said input signal.

Claim 44

The combination of claim 36 wherein said filter is a three pole Paynter filter having fast time domain response.

Claim 45

The combination of claim 33 wherein said second and third counters each provide a time delay in accordance with said predetermined maximum count, said time delay being sufficient to overcome spurious noise signals.