Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
198 words
In an apparatus for processing data contained in data response areas on a document or the like moving along a path through said apparatus and which document has a series of linearly equalLy spaced-apart timing marks each of which normally causes the activation of one or more data sensors so as to read said data response areas, the combination of: data sensors for reading bits of data contained in said data response areas as the document moves along said path by said data sensors, a timing mark sensor positioned so that said timing marks pass serially by it as said document moves along said path through said apparatus, said timing mark sensor causing a signal to be produced when a timing mark is sensed which signal can be utilized to actuate said data sensors, simulator means for repeatedly producing a signal that is in timed relationship to and simulates the signal produced by said timing mark sensor when it detects a timing mark, and a pulse priority detector for receiving the signals produced by said timing mark sensor and said simulator means and producing an output only at the time when the first of said signals is received.
Claim 2
Dependent Claim
198 words
In an apparatus for processing data contained in data response areas on a document or the like moving along a path through said apparatus and which document has a series of linearly equalLy spaced-apart timing marks each of which normally causes the activation of one or more data sensors so as to read said data response areas, the combination of: data sensors for reading bits of data contained in said data response areas as the document moves along said path by said data sensors, a timing mark sensor positioned so that said timing marks pass serially by it as said document moves along said path through said apparatus, said timing mark sensor causing a signal to be produced when a timing mark is sensed which signal can be utilized to actuate said data sensors, simulator means for repeatedly producing a signal that is in timed relationship to and simulates the signal produced by said timing mark sensor when it detects a timing mark, and a pulse priority detector for receiving the signals produced by said timing mark sensor and said simulator means and producing an output only at the time when the first of said signals is received.
Claim 3
Dependent Claim
58 words
In the apparatus of claim 1 in which said simulator means includes a pulse producing means for producing pulses at a regular predetermined rate, means to determine the number of pulses equivalent to the distance between two adjacent timing marks, and means to produce an output signal each time said pulse producing means produces said number of pulses.
Claim 4
Dependent Claim
92 words
In the apparatus of claim 2 in which there is provided means to start counting pulses produced by said pulse producing means when the first of said timing marks is detected by said timing mark sensor, means to stop counting said pulses when the second of said timing marks is detected, and means to compare said pulse count between the first and second timing marks with pulses produced by said pulse producing means and to produce an output signal each time said pulse count is again produced by said pulse producing means.
Claim 5
Dependent Claim
82 words
In the apparatus of claim 3 in which there is provided means to store the pulse count between the first and second timing marks, counter means is provided to count the pulses produced by said pulse producing means after detection of said second timing mark, and means is provided to compare said stored count with the count accumulated by said counter means and to produce an output signal when the count in said counter means reaches the count of said stored count.
Claim 6
Dependent Claim
34 words
In the apparatus of claim 4 in which said counter means is reset to zero count each time an output signal is produced either by said simulator means or by said timing mark sensor.
Claim 7
Dependent Claim
76 words
In the apparatus of claim 4 in which there is provided gate means between the output of said timing mark sensor and the input of said pulse priority detector, said gate means setting a predetermined range that is an absolute percentage of the time of each signal produced by said simulator means, said gate means providing an output to said pulse priority detector only when the output of said timing mark sensor is within said range.
Claim 8
Dependent Claim
31 words
In the apparatus of claim 6 in which said counter means is reset to zero each time an output signal is produced by said simulator means or by said gate means.
Claim 9
Dependent Claim
76 words
In the apparatus of claim 6 in which there is provided an error limit counter, said counter being connected to the output of said simulator means and producing an output signal whenever a predetermined number of outputs are received from said simulator means, and said error limit counter being also connected to the output of said gate means, said counter being reset to a zero count each time an output is received from said gate means.
Claim 10
Dependent Claim
76 words
In the apparatus of claim 1 in which there is provided gate means between the output of said timing mark sensor and the input of said pulse priority detector, said gate means setting a predetermined range that is an absolute percentage of the time of each signal produced by said simulator means, said gate means providing an output to said pulse priority detector only when the output of said timing mark sensor is within said range.
Claim 11
Dependent Claim
31 words
In the apparatus of claim 9 in which saiD counter means is reset to zero each time an output signal is produced by said simulator means or by said gate means.
Claim 12
Dependent Claim
76 words
In the apparatus of claim 9 in which there is provided an error limit counter, said counter being connected to the output of said simulator means and producing an output signal whenever a predetermined number of outputs are received from said simulator means, and said error limit counter being also connected to the output of said gate means, said counter being reset to a zero count each time an output is received from said gate means.