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US3831009A Expired / Lapsed US ⏱️ 0.0 years remaining

Timing system for optically scanned documents

Assignee: National Computer Systems Inc
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Filing: 1973-08-03
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Granted: 1974-08-20
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Expires: 1993-08-03
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Abstract

Abstract A system for use in document readers of the type in which manually-entered responses in predetermined data response areas on a document are optically scanned or read electronically as the document is conveyed at high speed. The data response areas are arranged in regularly spaced rows, and the timing of the scanning of each data row is usually controlled solely by preprinted regularly-spaced indicator marks along an edge of each document. The system of the invention measures the time interval between the initial indicator marks by counting timed pulses at a predetermined rate and these pulses are then used as a reference to control scanning of the data rows in the event that the timing indicator marks fail to produce the necessary signals to control the scanning of the data rows. The system also provides for continuous synchronizing of the timed pulses with those produced directly from the indicator marks.

Inventors

  • 👤 Millin J Mc

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 09:29
CPC Classifications
G; G06; G06K; G06K7/00; G06K7/01; G06K7/016; G06K7/0163

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 198 words
In an apparatus for processing data contained in data response areas on a document or the like moving along a path through said apparatus and which document has a series of linearly equalLy spaced-apart timing marks each of which normally causes the activation of one or more data sensors so as to read said data response areas, the combination of: data sensors for reading bits of data contained in said data response areas as the document moves along said path by said data sensors, a timing mark sensor positioned so that said timing marks pass serially by it as said document moves along said path through said apparatus, said timing mark sensor causing a signal to be produced when a timing mark is sensed which signal can be utilized to actuate said data sensors, simulator means for repeatedly producing a signal that is in timed relationship to and simulates the signal produced by said timing mark sensor when it detects a timing mark, and a pulse priority detector for receiving the signals produced by said timing mark sensor and said simulator means and producing an output only at the time when the first of said signals is received.
Claim 2
Dependent Claim 198 words
In an apparatus for processing data contained in data response areas on a document or the like moving along a path through said apparatus and which document has a series of linearly equalLy spaced-apart timing marks each of which normally causes the activation of one or more data sensors so as to read said data response areas, the combination of: data sensors for reading bits of data contained in said data response areas as the document moves along said path by said data sensors, a timing mark sensor positioned so that said timing marks pass serially by it as said document moves along said path through said apparatus, said timing mark sensor causing a signal to be produced when a timing mark is sensed which signal can be utilized to actuate said data sensors, simulator means for repeatedly producing a signal that is in timed relationship to and simulates the signal produced by said timing mark sensor when it detects a timing mark, and a pulse priority detector for receiving the signals produced by said timing mark sensor and said simulator means and producing an output only at the time when the first of said signals is received.
Claim 3
Dependent Claim 58 words
In the apparatus of claim 1 in which said simulator means includes a pulse producing means for producing pulses at a regular predetermined rate, means to determine the number of pulses equivalent to the distance between two adjacent timing marks, and means to produce an output signal each time said pulse producing means produces said number of pulses.
Claim 4
Dependent Claim 92 words
In the apparatus of claim 2 in which there is provided means to start counting pulses produced by said pulse producing means when the first of said timing marks is detected by said timing mark sensor, means to stop counting said pulses when the second of said timing marks is detected, and means to compare said pulse count between the first and second timing marks with pulses produced by said pulse producing means and to produce an output signal each time said pulse count is again produced by said pulse producing means.
Claim 5
Dependent Claim 82 words
In the apparatus of claim 3 in which there is provided means to store the pulse count between the first and second timing marks, counter means is provided to count the pulses produced by said pulse producing means after detection of said second timing mark, and means is provided to compare said stored count with the count accumulated by said counter means and to produce an output signal when the count in said counter means reaches the count of said stored count.
Claim 6
Dependent Claim 34 words
In the apparatus of claim 4 in which said counter means is reset to zero count each time an output signal is produced either by said simulator means or by said timing mark sensor.
Claim 7
Dependent Claim 76 words
In the apparatus of claim 4 in which there is provided gate means between the output of said timing mark sensor and the input of said pulse priority detector, said gate means setting a predetermined range that is an absolute percentage of the time of each signal produced by said simulator means, said gate means providing an output to said pulse priority detector only when the output of said timing mark sensor is within said range.
Claim 8
Dependent Claim 31 words
In the apparatus of claim 6 in which said counter means is reset to zero each time an output signal is produced by said simulator means or by said gate means.
Claim 9
Dependent Claim 76 words
In the apparatus of claim 6 in which there is provided an error limit counter, said counter being connected to the output of said simulator means and producing an output signal whenever a predetermined number of outputs are received from said simulator means, and said error limit counter being also connected to the output of said gate means, said counter being reset to a zero count each time an output is received from said gate means.
Claim 10
Dependent Claim 76 words
In the apparatus of claim 1 in which there is provided gate means between the output of said timing mark sensor and the input of said pulse priority detector, said gate means setting a predetermined range that is an absolute percentage of the time of each signal produced by said simulator means, said gate means providing an output to said pulse priority detector only when the output of said timing mark sensor is within said range.
Claim 11
Dependent Claim 31 words
In the apparatus of claim 9 in which saiD counter means is reset to zero each time an output signal is produced by said simulator means or by said gate means.
Claim 12
Dependent Claim 76 words
In the apparatus of claim 9 in which there is provided an error limit counter, said counter being connected to the output of said simulator means and producing an output signal whenever a predetermined number of outputs are received from said simulator means, and said error limit counter being also connected to the output of said gate means, said counter being reset to a zero count each time an output is received from said gate means.

References Cited (Backward Citations)

US3627990A Cited
US3474232A Cited
US3496342A Cited
US3752961A Cited
US3708655A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-08-19 1978-02-18 1978-08-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-08-19 1982-02-18 1982-08-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-08-19 1986-02-18 1986-08-20 $7700.00 Window Closed / Lapsed

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