Graphical data processor interface

Claim 2

An interface adapter for controLling a line by line video data flow along a data carrier between a central processor and a facsimile device by providing separate video and synchronization data, comprising a source of video line data, control means for generating a load data command and coupled to said source, a master control counter providing a a data rate signal signifying a data loading rate and a periodic scan rate signal signifying the synchronization of data transfer; first logic means coupled to said source, said counter and said control means and responsive to said load data command signal for loading said data line in a register, in accordance with said data rate signal, said register having a predetermined data capacity and providing a full signal indicative thereof; second logic means responsive to said scan rate signal and to said full signal for transferring said data line from said register to said data carrier.

Claim 3

The adaptor of claim 1 wherein said first logic means loads data in said register parallel by byte and said second logic means transfers said data serially by bit.

Claim 4

The adapter of claim 2 wherein said register includes a ring counter having a count capacity corresponding to a predetermined number of bytes, and a buffer register having a number of stages corresponding to said number of bytes, means coupling said ring counter to each of said buffer register stages for entering each sequentially received byte in a respective one of said stages in accordance with said ring counter count capacity, and further including third logic means coupling said buffer register to said data carrier for transferring said data line to said data carrier.

Claim 5

The adaptor of claim 3 wherein said third logic means includes a shift register coupled between said register and said data carrier, means coupling said counter to said shift register for providing a continuous shift signal to said shift register, said third logic means transferring said data line to said shift register for transferring said data line to said data carrier.

Claim 6

The adaptor of claim 4 and wherein said ring counter is automatically reset for each new set of data bytes, further including a fourth logic means responsive to a condition input for inhibiting the reset operation of said ring counter and for inhibiting said transfer.

Claim 7

The adaptor of claim 5 wherein said condition input includes manually operable switching means removing said central processor generated data flow from said adaptor.

Claim 8

The adaptor of claim 5 further including a test module, said test module providing one of said condition inputs and placing a predetermined plurality of test bits along said data carrier.

Claim 9

The adaptor of claim 7 wherein said test module derives said bits from said master control counter, and including means coupling said test bits to said shift register for injecting said bits along said data carrier.

Claim 10

The adaptor of claim 1 wherein said facsimile device includes a cutter drive circuit, said cutter drive circuit responsive to a first order for marking a facsimile transfer web for cutting said web at said mark, and to a second order for cutting said web immediately upon cessation of said data flow.

Claim 11

The adaptor of claim 3 wherein said facsimile device includes a form sense circuit for sensing the position of a transfer web form, and including further logic means for sensing said form sense upon command and providing a signal to said third logic means as a condition of said transfer.

Claim 12

The adaptor of claim 9 wherein said cutter device circuit includes means coupled thereto for varying the cutting force said cutter drive circuit applies to cut said transfer web.

Claim 13

An interface adaptor for controlling a line by line video data flow along a data carrier between a central processor and a facsimile device by providing separate video and sync data, comprising a master control counter providing a data sync signal, a data rate signal, a scan rate signal, and a shift signal, a Buffer having a predetermined bit capacity and supplying a full signal upon achieving said capacity, a shift register responsive to said shift signal for continually shifting the contents thereof along said data carrier, a control logic, said control logic including first logic means response to an initiating order and to said data rate signal to begin loading a line of data in said buffer at said data rate, second logic means responsive to said sync signal and to said full signal for conditioning a third logic means, said third logic means in said conditioned state responsive to said scan rate signal for transferring the contents of said buffer to said shift register, said shift register thereby shifting said data line out along said data carrier.

Claim 14

An interface adaptor for controlling a line by line video data flow along a data carrier between a central processor and a facsimile device by providing separate video and sync data, comprising a master control counter providing a data sync signal, a data rate signal, a scan rate signal, and a shift signal, a Buffer having a predetermined bit capacity and supplying a full signal upon achieving said capacity, a shift register responsive to said shift signal for continually shifting the contents thereof along said data carrier, a control logic, said control logic including first logic means response to an initiating order and to said data rate signal to begin loading a line of data in said buffer at said data rate, second logic means responsive to said sync signal and to said full signal for conditioning a third logic means, said third logic means in said conditioned state responsive to said scan rate signal for transferring the contents of said buffer to said shift register, said shift register thereby shifting said data line out along said data carrier.

Claim 15

The adaptor of claim 12 wherein said first logic means loads data in said register parallel by byte and said shift register transfers said data serially by bit.

Claim 16

The adaptor of claim 13 wherein said buffer includes a ring counter having a count capacity corresponding to a predetermined number bytes, and a buffer register having a number of stages corresponding to said number of bytes, means coupling said ring counter to each of said buffer register stages for entering each sequentially received byte in a respective one of said stages in accordance with said ring counter count capacity, and means coupling said third logic means to said buffer register for transferring said data line to said data carrier.

Claim 17

The adaptor of claim 12 wherein said third logic means includes a shift register coupled between said register and said data carrier means coupling said counter to said shift register for providing a continuous shift signal to said shift register, said third logic means transferring said said data line to said shift register for transferring said data line to said data carrier.

Claim 18

The adaptor of claim 15 and wherein said ring counter is automatically reset for each new set of data bytes, further including a fourth logic means responsive to a condition input for inhibiting the reset operation of said ring counter and for inhibiting said transfer.

Claim 19

The adaptor of claim 16 wherein said condition input includes manually operable switching means removing said central processor generated data flow from said adaptor.

Claim 20

The adaptor of claim 16 further including a module, said test module providing one of said condition inputs and placing a predetermined plurality of test bits along said data carrier.

Claim 21

The adaptor of claim 18 wherein said test module devices said bits from said master control counter, and including means coupling said test bits to said shift register for injecting said bits along said data carrier.

Claim 22

The adaptor of claim 12 wherein said facsimile device includes a cutter drive circuit, said cutter device circuit responsive to a first order for marking a facsimile transfer web for cutting said web at said mark, and to a second order for cutting said web immediately upon cessation of said data flow.

Claim 23

The adaptor of claim 20 wherein said cutter drive circuit includes means coupled thereto for varying the cutting force said cutter drive circuit applies to cut said transfer web.

Claim 24

The adaptor of claim 12 wherein said facsimile device includes a form sense circuit for sensing the position of a transfer web form, and including further logic means for sensing said form sense upon command and providing a signal to said third logic means as a condition of said transfer.

Claim 25

A graphic communication system comprising: facsimile system means for receiving graphic information representative of information on a document or the like, said facsimile system means comprising: scanner means for generating said graphic information to be transmitted representative of information on said document or the like, and printer means for creating a facsimile record in accordance with said received graphic information wherein said graphic information includes dAta synchronizing and supervisory control signals; computer means for generating said graphic information, said computer means being an electronic data processing system capable of internal electrical operations according to a predetermined program, and electrical interface means coupled between said facsimile system means and said computer means for converting said graphic information into interface signal formats compatible with the operation of said computer means and said facsimile system means, said electrical interface means comprising: a subcontroller for intercoupling orders and data lines with said computer means, a master control counter generating at predetermined count positions a first signal representing the rate of data received, a second signal representing the end of a data line, a third signal representing the end of a scan, a fourth signal corresponding to a line sync signal, and a fifth signal corresponding to a shift rate, a buffer having a predetermined count capacity and providing a full signal upon achievement thereof, a shift register, and a control logic circuit, said control logic responsive to an initiating order from said subcontroller and in turn derived from said computer for providing an initiating signal to said facsimile system, and to said first signal and said initiation order for loading a data line into said buffer, said buffer generating said full signal in response to full loading thereof, said facsimile system responsive to said initiating signal and said fourth signal for providing a plurality of status signals indicating said system is ready to operate, said control logic responsive to said status signals, said full signal, and the next of said third signals after said full signal for generating a transfer signal, said shift register responsive to said fifth signal for continuously shifting the contents thereof to a data carrier, said buffer responsive to said transfer signal for transferring the data line from said buffer to said shift register, said shift register thereby shifting said data line along said data carrier.

Claim 26

A graphic communication system comprising: facsimile system means for receiving graphic information representative of information on a document or the like, said facsimile system means comprising: scanner means for generating said graphic information to be transmitted representative of information on said document or the like, and printer means for creating a facsimile record in accordance with said received graphic information wherein said graphic information includes dAta synchronizing and supervisory control signals; computer means for generating said graphic information, said computer means being an electronic data processing system capable of internal electrical operations according to a predetermined program, and electrical interface means coupled between said facsimile system means and said computer means for converting said graphic information into interface signal formats compatible with the operation of said computer means and said facsimile system means, said electrical interface means comprising: a subcontroller for intercoupling orders and data lines with said computer means, a master control counter generating at predetermined count positions a first signal representing the rate of data received, a second signal representing the end of a data line, a third signal representing the end of a scan, a fourth signal corresponding to a line sync signal, and a fifth signal corresponding to a shift rate, a buffer having a predetermined count capacity and providing a full signal upon achievement thereof, a shift register, and a control logic circuit, said control logic responsive to an initiating order from said subcontroller and in turn derived from said computer for providing an initiating signal to said facsimile system, and to said first signal and said initiation order for loading a data line into said buffer, said buffer generating said full signal in response to full loading thereof, said facsimile system responsive to said initiating signal and said fourth signal for providing a plurality of status signals indicating said system is ready to operate, said control logic responsive to said status signals, said full signal, and the next of said third signals after said full signal for generating a transfer signal, said shift register responsive to said fifth signal for continuously shifting the contents thereof to a data carrier, said buffer responsive to said transfer signal for transferring the data line from said buffer to said shift register, said shift register thereby shifting said data line along said data carrier.

Claim 27

The system of claim 23 wherein said buffer receives data in the form of parallel by byte information and said shift register shifts data out in a serial by bit manner, said buffer including a transfer gate responsive to said transfer signal for transferring the contents of said buffer to said shift register.

Claim 28

The system of claim 23 wherein said buffer includes a ring counter having a count capacity corresponding to a predetermined number bytes, and a buffer register having a number of stages corresponding to said number of bytes, means coupling said ring counter to each of said buffer register stages for entering each sequentially receiving byte in a respective one of said stages in accordance with said ring counter count capacity, and means coupling said third logic means to said buffer register for transferring said data line to said data carrier.

Claim 29

The system of claim 25 wherein said ring counter is automatically reset for each new group of data bytes, said control logic further including means responsive to a condition input for inhibiting the reset operation of said ring counter and for inhibiting said transfer.

Claim 30

The system of claim 26 wherein said condition input includes manually operable switching means.

Claim 31

The system of claim 27 further including a module, said test module providing one of said condition inputs and placing a predetermined plurality of test bits along said data carrier for use in said printer.

Claim 32

The system of claim 28 wherein said test module derives test bits from said master control counter, and including means coupling said test bits to said shift register for injecting said bits along said data carrier.

Claim 33

The system of claim 23 wherein said facsimile device includes a cutter drive circuit, said cutter drive circuit responsive to a first order for marking a facsimile transfer web for cutting said web at said mark, and to a second order for cutting said web immediately upon cessation of said data flow.

Claim 34

The system of claim 30 wherein said cutter drive circuit includes means coupled thereto for varying the cutting force said cutter drive circuit applies to cut said transfer web.

Claim 35

The system of claim 23 wherein said facsimile device includes a form sense circuit for sensing the position of a transfer web form, and including further logic means for sensing said form sense upon command and providing a signal to said third logic means as a condition of said transfer.