Serial binary square root apparatus

Claim 2

Serial binary square root apparatus comprising, in combination: first means for supplying a radicand word Io in serial data bit format LSB first and having N bits; second means for storing J and for initially setting J equal to zero where J represents the accumulated quotient of a square root operation; third means for generating M where M equals 1/2 (n 2) and n equals the individual word time in a frame of N words; fourth means for circulating the radicand word Io as initially supplied and as modified by the square rooting operations within the apparatus N times during the square rooting operation; fifth means for subtracting M and J from I for each word of the frame where I is the remainder after each circulation occurring in the square root operation and at commencement of the square root operation equals Io and said fifth means providing a difference word output; sixth means for checking the difference word output and providing a sign signal when the difference word is positive; and gating means for inserting a logic 1 into said second means in a bit position corresponding to n when said sixth means produces the sign signal.

Claim 3

Apparatus as claimed in claim 1 comprising, in addition: means for checking the sign of Io and preventing operation of said gating means if Io is negative.

Claim 4

Apparatus as claimed in claim 1 wherein said fifth means includes: first and second word storage means; and further gating means for storing and doubling the value of one of the words I-M-J and I in accordance with the presence and absence of said sign signal in preparation for the next word circulation in the square rooting operation.

Claim 5

Serial binary square rooting apparatus for obtaining the square root of a serial binary word Io having N binary bits in an operation having a frame of N words comprising in combination: apparatus input means for supplying a serial binary word Io; first, second, and third multiple bit storage means, each including input and output means; first gating means, including first and second control means, first, second, and third input means and output means; means connecting said first, second, and third input means respectively of said first gating means to receive signals from said output means of said first and second multiple bit storage means and from said apparatus input means. means for supplying a control signal to said first control means of said first gating means to connect said third input means thereof to said output means thereof, during the first word of a frame; word summing means including first and second input means and output means; means connecting said output means of said first gating means to said input means of said first multiple bit storage means and to said first input means of said word summing means to supply words I thereto; second gating means, including control means, connected to said output means and said input means of said third multiple bit storage means to allow word circulation, said control means thereof for inserting predetermined logic bits into said third storage means in positions corresponding to the word position in the square rooting operation frame in accordance with received control signal inputs to form an accumulated square root quotient J; generating means for generating predetermined root extractor logic bits M; signal combining means connected to said generating means and to said input means of said third multiple bit storage means for receiving signals therefrom and supplying a logical combination thereof to said second input of said summing means; sign detecTion means connected to said output means of said summing means for providing an output control signal to said control means of said second gating means and to said second control means of said first gating means, the control signal supplied to said second control means enabling passage of the word from said second multiple bit storage means for the following word time; and means connecting the output means of said summing means to said input means of said second multiple bit storage means.

Claim 6

Serial binary square rooting apparatus for obtaining the square root of a serial binary word Io having N binary bits in an operation having a frame of N words comprising in combination: apparatus input means for supplying a serial binary word Io; first, second, and third multiple bit storage means, each including input and output means; first gating means, including first and second control means, first, second, and third input means and output means; means connecting said first, second, and third input means respectively of said first gating means to receive signals from said output means of said first and second multiple bit storage means and from said apparatus input means. means for supplying a control signal to said first control means of said first gating means to connect said third input means thereof to said output means thereof, during the first word of a frame; word summing means including first and second input means and output means; means connecting said output means of said first gating means to said input means of said first multiple bit storage means and to said first input means of said word summing means to supply words I thereto; second gating means, including control means, connected to said output means and said input means of said third multiple bit storage means to allow word circulation, said control means thereof for inserting predetermined logic bits into said third storage means in positions corresponding to the word position in the square rooting operation frame in accordance with received control signal inputs to form an accumulated square root quotient J; generating means for generating predetermined root extractor logic bits M; signal combining means connected to said generating means and to said input means of said third multiple bit storage means for receiving signals therefrom and supplying a logical combination thereof to said second input of said summing means; sign detecTion means connected to said output means of said summing means for providing an output control signal to said control means of said second gating means and to said second control means of said first gating means, the control signal supplied to said second control means enabling passage of the word from said second multiple bit storage means for the following word time; and means connecting the output means of said summing means to said input means of said second multiple bit storage means.

Claim 7

Apparatus as claimed in claim 4 comprising, in addition, further sign detection means connected to said apparatus input means and to said second gating means for enabling passage of logic 1 bits to said third multiple bit storage means only when Io is a positive number.

Claim 8

Apparatus for obtaining a serial word square root from a serial word radicand Io over a time period of N serial words comprising a word frame comprising, in combination: means for generating J; means for generating M; means for comparing I with M + J for each word of a frame of N words used in obtaining a square root wherein: I the remainder after a given word of the frame Io - J2 J the accumulated square root quotient at a given word of the frame M a root extractor squared N number of bits in a word; means, connected to said means for comparing and to said means for generating J and M, for generating and thereafter doubling I after each comparison when I is less than M + J and in the alternative for doubling I - M - J after each comparison when I is equal to or greater than M + J and additionally inserting a logic 1 into said means for generating J corresponding in bit position in the J word with total number of comparisons performed in the frame; and means, connected to said means for generating J, for outputting Square Root Io after the final comparison of the frame.

Claim 9

Apparatus for obtaining a serial word square root from a serial word radicand Io over a time period of N serial words comprising a word frame comprising, in combination: means for generating J; means for generating M; means for comparing I with M + J for each word of a frame of N words used in obtaining a square root wherein: I the remainder after a given word of the frame Io - J2 J the accumulated square root quotient at a given word of the frame M a root extractor squared N number of bits in a word; means, connected to said means for comparing and to said means for generating J and M, for generating and thereafter doubling I after each comparison when I is less than M + J and in the alternative for doubling I - M - J after each comparison when I is equal to or greater than M + J and additionally inserting a logic 1 into said means for generating J corresponding in bit position in the J word with total number of comparisons performed in the frame; and means, connected to said means for generating J, for outputting Square Root Io after the final comparison of the frame.