US3829653A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-character electronic display
Assignee: Texas Instruments Inc
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Filing: 1971-01-19
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Granted: 1974-08-13
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Expires: 1991-01-19
Abstract
Abstract Disclosed are multiple character electronic display devices utilizing plurality of character matrices, each of which includes plurality of thermally isolated semiconductor mesas which are heated by current passed through a resistance. The current in each mesa is controlled by a transistor formed therein, and such transistors may have a common collector voltage and a common emitter voltage supply lead which may be individually closed by a switch to enable a desired character. The bases of the transistors of corresponding mesas in all of the character matrices may be connected to common control lines to that all character matrices may be controlled by the same character generator. A particular diffusion pattern for the individual elements of the matrices is also disclosed which utilizes an extended collector transistor having a longitudinally extending, double diffused tunnel to provide cross connections from the control lines to the base contacts of the elements of an array.
Inventors
- 👤 C Ensminger
- 👤 E Ruggiero
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 05:21
CPC Classifications
B; B41; B41J; B41J2/00; B41J2/315; B41J2/32; B41J2/35; B41J2/355; G; G09; G09G; G09G3/00; G09G3/04; G09G3/16
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
157 words
In a switching matrix, the combination of: a plurality of sets of transistors, each set having a corresponding number, first circuit means common to the collectors of the transistors of each set, including a resistive heating element connecting the collectors of the respective transistors to a common point, second circuit means common to the emitters of the transistors of each set, including a resistive heating element connecting the collectors of the respective transistors to a common point, and a separate control line common to the bases of the corresponding transistors of each set of transistors whereby each set of transistors may be selectively enabled by connecting a supply voltage between the first and second circuit means for the set and the individual transistors in the enabled set may be turned on by a voltage applied to the respective control line, the resistive heating elements of each set being arrayed in a character matrix of an electronic display.
Claim 2
Dependent Claim
157 words
In a switching matrix, the combination of: a plurality of sets of transistors, each set having a corresponding number, first circuit means common to the collectors of the transistors of each set, including a resistive heating element connecting the collectors of the respective transistors to a common point, second circuit means common to the emitters of the transistors of each set, including a resistive heating element connecting the collectors of the respective transistors to a common point, and a separate control line common to the bases of the corresponding transistors of each set of transistors whereby each set of transistors may be selectively enabled by connecting a supply voltage between the first and second circuit means for the set and the individual transistors in the enabled set may be turned on by a voltage applied to the respective control line, the resistive heating elements of each set being arrayed in a character matrix of an electronic display.
Claim 3
Dependent Claim
34 words
The combination of claim 1 wherein: each resistive heating element and the transistor to which it is connected are formed by a semiconductor mesa, and the semiconductor mesas are isolated by a thermal discontinuity.
Claim 4
Dependent Claim
160 words
The combination of claim 2 wherein: the semiconductor mesas are mounted on a supporting chip by a layer of thermally insulating material in at least one row with the transistors adjacent the insulating material, each mesa includes an extended collector region extending normal to the row, a collector contact formed at one end of the collector region, a base region and an emitter region formed at the other end of the collector region, with a base contact between the collector contact and an emitter contact, an insulating layer over the mesas having collector, base and emitter contact openings, one level of electrical leads including a collector lead extending over the collector contact openings of the mesas in the row, an emitter lead extending over the emitter contact openings of the mesas of the row, and a plurality of control leads disposed between the collector and emitter leads, and another level of interconnections connecting selected control leads to selected base contacts.
Claim 5
Dependent Claim
18 words
The combination of claim 3 wherein: said another level of interconnections comprises a tunnel in each semiconductor mesa.
Claim 6
Dependent Claim
22 words
The combination of claim 4 wherein: the tunnel is comprised of an emitter diffusion in a base diffusion in the collector region.
Claim 7
Dependent Claim
57 words
The combination of claim 3 wherein: there are a plurality of rows of mesas arrayed to form a plurality of character matrices, and the mesas in alternate rows are inverted such that the collector and emitter contacts of the transistors in each row are adjacent the collector and emitter contacts, respectively, of the adjacent rows of mesas.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-08-12 | 1978-02-11 | 1978-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-08-12 | 1982-02-11 | 1982-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-08-12 | 1986-02-11 | 1986-08-13 | $7700.00 | Window Closed / Lapsed |