Sonar reverberation simulator

Claim 2

A sonar reverberation simulator comprising: a. a digitized signal storage memory means, first recirculation shift register means, first logic and gating means and timing circuit means for transferring original sonar input signals to digital form, sequence sampling the same and storing each sample of each sequence at a different address in said memory means for individual replica readouts; b. signal generator means and second logic means for developing and passing through said register means and said first logic means to said storage memory means a series of pulses representative of reverberation echoes of said original signals; and c. multiplying digital to analog converter means for converting the digital output of said memory means to analog output signals.

Claim 3

Apparatus according to claim 1, a. said generator means comprising a random signal generator.

Claim 4

Apparatus according to claim 2, a. said generator means comprising a programmed signal generator to develop signals representative of a specific target.

Claim 5

Apparatus according to claim 1, including a. a second recirculating shift register having the same number of stages as said first shift register means and connected for coordinated action therewith; b. an amplitude control number generator means and transfer logic means for inserting digital numbers in said second shift register; and c. second digital to analog converter means connected to said multiplying converter means to provide amplitude control reference signals at the beginning of each readout sequence.

Claim 6

Apparatus according to claim 1, including a. a third recirculating shift register having the same number of stages as said first and second shift register means and connected for coordinated action therewith; b. additional number generator means and logic means for inserting digital numbers in said third shift register; c. a plurality of digital comparator units connected each to receive as one input the output of said third shift register; d. a reference number generator for each comparator unit to provide a second different numbered reference input to each comparator unit; and e. a plurality of analog gate means each connected to receive one input from an associated of said digital comparators and a second common input from said multiplying converter means to provide outputs forming a plurality of azimuth channels.

Claim 7

A sonar reverberation simulator comprising a. analog to digital means for converting an original transmitted input signal pulse representative of a sonar ping into an original digital replica; b. an adjustable rate pulse generator for developing additional digital signals representative of sonar echoes which would be received from spaced scatterers to provide overlapping signals of the original transmitted signal as additional replica signals; c. a first logic means; d. a second logic means; e. a first recirculating gated shift register for generating overlapping sequences of digital numbers responsive to inputs from said pulse generator respectively through said first and second logic means; f. random access memory means for storing digitized samples of said original signal; g. a time regulated sample rate circuit including an address counter connected to gate said first logic means to time sample the input of said replica signals and direct each sequential sample to a different address in said memory means; h. digital address comparator means connected to said address counter and to said shift register to provide a gate signal controlling the signals passed through said recirculation loop circuit; and i. digital to analog conversion means connected to receive the read data output of said memory means and produce an analog signal representative of the summation of said replica signals.

Claim 8

A sonar reverberation simulator comprising a. analog to digital means for converting an original transmitted input signal pulse representative of a sonar ping into an original digital replica; b. an adjustable rate pulse generator for developing additional digital signals representative of sonar echoes which would be received from spaced scatterers to provide overlapping signals of the original transmitted signal as additional replica signals; c. a first logic means; d. a second logic means; e. a first recirculating gated shift register for generating overlapping sequences of digital numbers responsive to inputs from said pulse generator respectively through said first and second logic means; f. random access memory means for storing digitized samples of said original signal; g. a time regulated sample rate circuit including an address counter connected to gate said first logic means to time sample the input of said replica signals and direct each sequential sample to a different address in said memory means; h. digital address comparator means connected to said address counter and to said shift register to provide a gate signal controlling the signals passed through said recirculation loop circuit; and i. digital to analog conversion means connected to receive the read data output of said memory means and produce an analog signal representative of the summation of said replica signals.

Claim 9

Apparatus according to claim 6, including a. an address comparator connected to said address counter and said recirculation shift register and having an ''''equal to'''' output for opening said gated loop circuit to end a particular readout sequence when the number recirculated through said shift register is equal to that of the last address in said memory means in which data is stored.

Claim 10

Apparatus according to claim 6, including a. a second recirculating shift register having the same number of stages as said first shift register means and connected for coordinated action therewith; b. an amplitude control number generator means and transfer logic means for inserting digital numbers in said second shift register; and c. second digital to analog converter means connected to said multiplying converter means to provide amplitude control reference signals at the beginning of each readout sequence.

Claim 11

Apparatus according to claim 6, including a. a third recirculating shift register having the same number of stages as said first and second shift register means and connected for coordinated action therewith; b. additional number generator means and logic means for inserting digital numbers in said third shift register; c. a plurality of digital comparator units connected each to receive as one input the output of said third shift register; d. a reference number generator for each comparator unit to provide a second different numbered reference input to each comparator unit; anD e. a plurality of analog gate means each connected to receive one input from an associated of said digital comparators and a second common input from said multiplying converter means to provide outputs forming a plurality of azimuth channels.

Claim 12

Apparatus according to claim 6, a. said generator means comprising a random signal generator.

Claim 13

Apparatus according to claim 6, a. said generator means comprising a programmed signal generator to develop signals representative of a specific target.