US3828326A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Adapter for interfacing a programmable controller to a data processor channel
Assignee: International Business Machines Corp
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Filing: 1973-04-18
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Granted: 1974-08-06
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Expires: 1993-04-18
Abstract
Abstract An adapter interfaces a computer channel to a single controller normally capable of both controlling a device and meeting the channel response requirements. The adapter detects times when the controller cannot communicate with the channel, inhibits this function of the controller, and itself carries out an altered channel communication procedure in simple logic circuits.
Inventors
- 👤 K Cash
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 02:48
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/122; G06F13/14; G06F13/20; G06F13/24
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
211 words
An adapter for interfacing a single programmable controller to a channel of a data processor, said single controller being operative both to control a peripheral device and to communicate with said channel, said adapter comprising: receiver means for accepting outbound signals from said channel; driver means for transmitting inbound signals from said adapter and from said controller to said channel; interrupt means responsive to a predetermined combination of said outbound signals indicating that said channel has addressed said device, said interrupt means producing an interrupt signal enabling said controller to produce a plurality of said inbound signals according to one of a number of different procedures, one of said procedures being a first procedure indicating that said device is busy; inhibiting means for disabling said interrupt means in responsive to a busy bit from said controller, said busy bit indicating that said controller is temporarily unable to produce said inbound signals according to said first procedure; and logic means responsive both to said busy bit and to said combination of outbound signals indicating that said channel has addressed said device, for producing a second plurality of said inbound signals according to a second predetermined procedure, said second procedure indicating that said device is busy, but being different from said first procedure.
Claim 2
Dependent Claim
211 words
An adapter for interfacing a single programmable controller to a channel of a data processor, said single controller being operative both to control a peripheral device and to communicate with said channel, said adapter comprising: receiver means for accepting outbound signals from said channel; driver means for transmitting inbound signals from said adapter and from said controller to said channel; interrupt means responsive to a predetermined combination of said outbound signals indicating that said channel has addressed said device, said interrupt means producing an interrupt signal enabling said controller to produce a plurality of said inbound signals according to one of a number of different procedures, one of said procedures being a first procedure indicating that said device is busy; inhibiting means for disabling said interrupt means in responsive to a busy bit from said controller, said busy bit indicating that said controller is temporarily unable to produce said inbound signals according to said first procedure; and logic means responsive both to said busy bit and to said combination of outbound signals indicating that said channel has addressed said device, for producing a second plurality of said inbound signals according to a second predetermined procedure, said second procedure indicating that said device is busy, but being different from said first procedure.
Claim 3
Dependent Claim
95 words
The adapter of claim 1, wherein said interrupt means includes comparator means for producing an identifying signal in response to predetermined Bus Out signals indicating that said device has been addressed, and gating means responsive to said identifying signal and to an Address Out signal, said Bus Out and Address Out signals being included in said predetermined combination of outbound signals; and wherein said logic means includes a latch means responsive to the simultaneous presence of said identifying signal, said Address Out signal, and said busy bit for producing said second plurality of inbound signals.
Claim 4
Dependent Claim
32 words
The adapter of claim 2, wherein said latch means is further responsive to the simultaneous presence of Select Out and Hold Out signals which are further included in said predetermined outbound signals.
Claim 5
Dependent Claim
26 words
The adapter of claim 3, wherein said latch means is disabled by the absence of at least one of said Select Out and Hold Out signals.
Claim 6
Dependent Claim
43 words
The adapter of claim 2, wherein said inbound signals comprise a bus group and a tag group for controlling the interpretation of said bus group by said channel, said latch means being operative to produce at least one signal in each said group.
Claim 7
Dependent Claim
27 words
The adapter of claim 5, wherein said latch means produces a Bus In signal in said bus group and a Status In signal in said tag group.
Claim 8
Dependent Claim
34 words
The adapter of claim 5, wherein said bus group carries eight data bits labelled 0-7, and wherein said latch means is operative to produce a signal only on bit 3 of said bus group.
Claim 9
Independent Claim
158 words
A method of interfacing a data-processor channel having fixed response-time requirements to a single programmable controller which is normally capable of both controlling a peripheral device and processing channel signals for communicating with said channel, but which may temporarily enter an uninterruptible instruction sequence while controlling said device, so as to become unable to satisfy said requirements, said method comprising the steps of: producing from said channel signals an interrupt signal for enabling said controller to communicate with said channel according to a normal procedure; executing an instruction in said controller prior to said uninterruptible sequence for producing A continuous busy signal during said sequence; inhibiting said interrupt signal in response to said busy signal; communicating with said channel according to an altered procedure by producing predetermined ones of said channel signals in logic circuits outside said controller in response to said busy signal; and executing an instruction subsequent to said uninterruptible sequence for disabling said busy signal.
Claim 10
Independent Claim
158 words
A method of interfacing a data-processor channel having fixed response-time requirements to a single programmable controller which is normally capable of both controlling a peripheral device and processing channel signals for communicating with said channel, but which may temporarily enter an uninterruptible instruction sequence while controlling said device, so as to become unable to satisfy said requirements, said method comprising the steps of: producing from said channel signals an interrupt signal for enabling said controller to communicate with said channel according to a normal procedure; executing an instruction in said controller prior to said uninterruptible sequence for producing A continuous busy signal during said sequence; inhibiting said interrupt signal in response to said busy signal; communicating with said channel according to an altered procedure by producing predetermined ones of said channel signals in logic circuits outside said controller in response to said busy signal; and executing an instruction subsequent to said uninterruptible sequence for disabling said busy signal.
Claim 11
Dependent Claim
31 words
The method of claim 8, including the step of executing a further instruction subsequent to said uninterruptible sequence, said further instruction being operative to initiate an ending procedure to said channel.
References Cited (Backward Citations)
US3573741A
Cited
US3728693A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-08-05 | 1978-02-04 | 1978-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-08-05 | 1982-02-04 | 1982-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-08-05 | 1986-02-04 | 1986-08-06 | $7700.00 | Window Closed / Lapsed |