End mark controlled switching system and matrix

Claim 2

A switching system controlled by applying and removing respective electrical end marking signals to and from an inlet and an outlet thereof, said system comprising the combination of a three terminal switching means having first and second terminals coupled between said inlet and said outlet, bias means coupled to a third terminal of said switching means for applying a bias thereto, and control means coupled between said first terminal and said bias means and responsive to the application of one of said end marking signals for controlling the bias applied to said third terminal by said bias means in accordance with a predetermined timing sequence so that said bias is changed a short time after the application of said end marking signal from a first level selected to enable said switching means to a second level selected to inhibit said switching means, whereby said switching means responds to the application of said end marking signals to said inlet and outlet only if said signals satisfy the predetermined timing relationship.

Claim 3

The switching system of claim 1 further including means for applying information bearing signals to said inlet for transmission between said inlet and outlet through said switching means when said switching means is in a conductive state.

Claim 4

The switching system of claim 2 wherein said switching means is switched to said conductive state when end marking signals which satisfy said predetermined timing relationship are applied to said inlet and said outlet.

Claim 5

The switching system of claim 1 wherein said bias means includes a bias supply source and impedance means coupled between said source and said third terminal of said switching means, and said control means includes switch Means coupled to said impedance means and means coupled between said first terminal and said switch means for switching said switch means from one state to another so as to inhibit said switching means in response to but with a slight delay following the application of said one end marking signal.

Claim 6

The switching system of claim 4 wherein said switch means is coupled in series with said impedance means for controlling the flow of current therethrough, and said switch means is switched from a conductive state to a non-conductive state to inhibit said switching means.

Claim 7

The switching system of claim 4 wherein said switch means is coupled in parallel with said impedance means for controlling the amount of voltage dropped thereacross, and said switch means is swithced from a non-conductive state to a conductive state to inhibit said switching means.

Claim 8

The switching system of claim 1 wherein said causes means cuases said bias means to maintain the bias applied to the third terminal of said switching means at substantially said second level at all times except for a brief period following the application of said one end marking signal, whereby said switching means is enabled to respond to said end marking signals only for said brief period.

Claim 9

The switching system of claim 7 wherein said period is long relative to the time required for said switching means to respond to said end marking signals, whereby said switching means responds when said end marking signals are present during said period independently of any rate effect switching characteristics said switching means may possess.

Claim 10

An end mark controlled switching system comprising the combination of a three terminal, four layer thyristor having an anode, a cathode, and a gate brought out from the layer adjacent said anode so that there is an anode-gate junction defined therebetween; bias means coupled to said gate for applying a bias voltage thereto; end marking means coupled to said anode and cathode for marking said anode by applying a predetermined voltage thereto and for marking said cathode by completing a low impedance return path to ground therefrom; and control means coupled between said bias means and the cathode of said thyristor and responsive to the marking of said cathode for inhibiting said thyristor in accordance with a predetermined timing sequence by increasing the bias voltage applied to said gate a short time after the marking of said cathode to a level sufficient to preclude said anode-gate junction from being forward biased by the application of said anode end mark, whereby said thyristor switches into conduction in response to the marking of its anode and cathode only if said end marks satisfy the predetermined timing relationship.

Claim 11

An end mark controlled switching system comprising the combination of a three terminal, four layer thyristor having an anode, a cathode, and a gate brought out from the layer adjacent said anode so that there is an anode-gate junction defined therebetween; bias means coupled to said gate for applying a bias voltage thereto; end marking means coupled to said anode and cathode for marking said anode by applying a predetermined voltage thereto and for marking said cathode by completing a low impedance return path to ground therefrom; and control means coupled between said bias means and the cathode of said thyristor and responsive to the marking of said cathode for inhibiting said thyristor in accordance with a predetermined timing sequence by increasing the bias voltage applied to said gate a short time after the marking of said cathode to a level sufficient to preclude said anode-gate junction from being forward biased by the application of said anode end mark, whereby said thyristor switches into conduction in response to the marking of its anode and cathode only if said end marks satisfy the predetermined timing relationship.

Claim 12

The switching system of claim 9 wherein the anode and cathode of said thyristor are connected between an inlet and an outlet, and wherein said inlet includes means for applying information bearing signals which are transmitted to said outlet through the anode-cathode circuit of said thyristor when said thyristor is in its conductive state.

Claim 13

The switching system of claim 9 wherein the anode and cathode of said thyristor are connected between an inlet and an outlet, and wherein the anode-cathode circuit of said thyristor completes at least a voice grade transmission path between said inlet and said outlet when said thyristor is in its conductive state.

Claim 14

The switching system of claim 11 wherein said inlet includes means for applying analog signals for transmission to said outlet through the anode-cathode circuit of said thyristor when said thyristor is in its conductive state.

Claim 15

The switching system of claim 9 wherein said thyristor and said control means are included in a single integrated circuit.

Claim 16

The switching system of claim 9 wherein said bias means includes a bias supply source selected to have an output voltage which is high relative to the voltage of said anode end mark, and an impedance means coupled between said bias supPly source and the gate of said thyristor; and said control means includes switch means coupled to said impedance means for controlling the amount of voltage dropped thereacross, and input means coupled between the cathode of said thyristor and said switch means for switching said switch means from one state to another in response to but with a slight delay following the marking of said cathode, whereby said thyristor is thereafter inhibited by having its gate bias voltage held at substantially the output voltage of said bias supply source at least until said cathode end mark is removed.

Claim 17

The switching system of claim 14 wherein the bias voltage applied to the gate of said thyristor is held by said control means at substantially the output voltage of said bias supply source at all times except for a brief period following the end marking of said cathode during which said bias voltage is reduced to a level which is sufficiently below the voltage of said anode end mark that the anode-cathode junction of said thyristor is forward biased to cause said thyristor to switch to its conductive state if an anode end mark is present during said period.

Claim 18

The switching system of claim 15 wherein said period is long relative to a predetermined turn-on time for said thyristor, whereby said thyristor switches into conduction if its anode is end marked at the time its cathode is end marked independently of the rate of change of its anode-cathode voltage.

Claim 19

The switching system of claim 15 wherein said switch means includes a transistor which has a collector-emitter circuit which is connected in series with said impedance means and a base coupled to said input means, said input means holding said transistor in a non-conductive state to thereby prevent current flow through said impedance means at all times except for said brief period following the end marking of the cathode of said thyristor, whereby the bias voltage applied to the gate of said thyristor is held at substantially the output voltage of said bias supply source at all times except for said brief period.

Claim 20

The switching system of claim 17 wherein said thyristor, said impedance means, and said transistor are included in the same integrated circuit.

Claim 21

The switching system of claim 17 wherein said impedance means comprises a field effect transistor having a sourcedrain circuit connected between said bias supply source and the gate of said thyristor and a grounded base, and said control means further includes means connected between the gate of said thyristor and the collector-emitter circuit of said transistor for maintaining a predetermined bias voltage on the gate of said thyristor when the last mentioned transistor is in its conductive state.

Claim 22

The switching system of claim 19 wherein said thyristor, said field effect transistor, said last mentioned transistor, and the means connected between the gate of said thyristor and the collector-emitter circuit of said last mentioned transistor are included in the same integrated circuit.

Claim 23

The switching system of claim 17 wherein said input means includes second and third transistors having parallel collectoremitter circuits connected to said bias supply source with the base of the second transistor connected to the cathode of said thyristor and the base of the third transistor connected to a fixed reference voltage means so that the second transistor is conductive and the third transistor is non-conductive when the voltage on the thyristor cathode is above said fixed reference voltage, and the second transistor is non-conductive and the third transistor is conductive when the voltage on the thyristor cathode is below said fixed reference voltage, and means responsive to conduction of said third transistor for reducing the first transistor conductive when the voltage on the thyristor cathode is below said fixed reference voltage.

Claim 24

The switching system of claim 21 wherein said means for rendering the first transistor conductive includes a fourth transistOr having a collector-emitter circuit connected to the base of said first transistor and a base connected to the collector-emitter circuit of said third transistor for rendering said fourth and first transistors conductive in response to conduction of said third transistor.

Claim 25

The switching system of claim 21 which includes means for rendering said first transistor nonconductive at the end of said brief period following the end marking of the cathode of said thyristor regardless of whether said third transistor is conductive at the end of said brief period.

Claim 26

The switching system of claim 23 wherein said means for rendering said first transistor nonconductive includes a fifth transistor having a collector-emitter circuit connected between the base and the collector-emitter circuit of said first transistor and a base connected to the collector-emitter circuit of said fourth transistor, whereby conduction of said fifth transistor renders said first transistor non-conductive, and a capacitor connected to the base of the fifth transistor for delaying the conduction of said fifth transistor until said capacitor accumulates a predetermined charge in response to the conduction of said fourth transistor.

Claim 27

The switching system of claim 24 which includes a sixth transistor having a collector-emitter circuit connected to said capacitor and a base connected to a fixed reference voltage means for discharging said capacitor whenever said fourth transistor is non-conductive.

Claim 28

The switching system of claim 21 wherein said fixed reference voltage means includes circuit means connected to said bias supply source for furnishing said fixed reference voltage to a plurality of said input means coupled to a plurality of rows of thyristors.

Claim 29

The switching system of claim 25 wherein the fixed reference voltage means connected to said sixth transistor and the fixed reference voltage means connected to said third transistor comprise a single circuit means connected to said bias supply source for furnishing fixed reference voltages of two different values to a plurality of said input means coupled to a plurality of rows of thyristors.

Claim 30

The switching system of claim 21 wherein said thyristor, said impedance means, and said transistors are all included in the same integrated circuit.

Claim 31

The switching system of claim 14 wherein said input means is coupled to the cathode of said thyristor by a Darlington pair in an emitter follower configuration, whereby the loading of said thyristor by said control means is negligible.

Claim 32

The switching system of claim 14 wherein said switch means includes a first transistor having a collector-emitter circuit connected in parallel with said impedance means and a base and a second transistor having a collector-emitter circuit connected in series with said impedance means and a base; and wherein said input means is coupled to the bases of said first and second transistors and responds to the end marking of said cathode to hold said first and second transistors in non-conductive and conductive states, respectively, for a brief period following the cathode end marking.

Claim 33

An end mark controlled switching matrix comprising the combination of a plurality of three terminal, four layer thyristors each having an anode, a cathode, and a gate brought out from the layer adjacent said anode so as to be separated therefrom by an anode-gate junction, said thyristors being connected in rows and columns as crosspoints between inlets and outlets of said matrix with each row including a group of thyristors which have their cathodes connected in common and their anodes separately connected and each column including another group of thyristors which have their anodes connected in common and their cathodes separately connected; means for end marking the anodes of the thyristors in each column by applying a predetermined voltage thereto and for end marking the cathodes of the thyristors in each row by completing a low impedance return path to ground therefrom; a respective bias means coupled to the gate of each of said thyristors and isolated from the gate of each of said other thyristors for applying a bias voltage thereto which is independent of the bias voltage applied to the gates of the other thryistors; and respective control means for the thyristors of each row; each of said control means being connected between the common cathodes and the gate bias means of the thyristors in a respective one of said rows and being responsive to the marking of said cathodes to inhibit any of the thyristors in said row that are in a non-conductive state when a predetermined period has been elapsed following the end marking of said cathodes.

Claim 34

An end mark controlled switching matrix comprising the combination of a plurality of three terminal, four layer thyristors each having an anode, a cathode, and a gate brought out from the layer adjacent said anode so as to be separated therefrom by an anode-gate junction, said thyristors being connected in rows and columns as crosspoints between inlets and outlets of said matrix with each row including a group of thyristors which have their cathodes connected in common and their anodes separately connected and each column including another group of thyristors which have their anodes connected in common and their cathodes separately connected; means for end marking the anodes of the thyristors in each column by applying a predetermined voltage thereto and for end marking the cathodes of the thyristors in each row by completing a low impedance return path to ground therefrom; a respective bias means coupled to the gate of each of said thyristors and isolated from the gate of each of said other thyristors for applying a bias voltage thereto which is independent of the bias voltage applied to the gates of the other thryistors; and respective control means for the thyristors of each row; each of said control means being connected between the common cathodes and the gate bias means of the thyristors in a respective one of said rows and being responsive to the marking of said cathodes to inhibit any of the thyristors in said row that are in a non-conductive state when a predetermined period has been elapsed following the end marking of said cathodes.

Claim 35

The switching matrix of claim 31 further including means for applying information bearing signals to the inlets of said matrix for transmission to selected outlets thereof via the anode-cathode circuits of said thyristors.

Claim 36

The switching matrix of claim 32 wherein said information bearing signals are analog signals, and the anode-cathode circuits of said thyristors provide at least voice grade transmission paths when said thyristors are in their conductive states.

Claim 37

The switching matrix of claim 31 wherein each of said control means inhibits the non-conductive thyristors in its respective row of the matrix by increasing the bias voltages applied to their gates to such a high level that their anode-gate junctions are prevented from being forward biased even if their anodes are later end marked.

Claim 38

The switching matrix of claim 31 wherein each of sad control means inhibits the non-conductive thyristors in its respective row of the matrix from switching to their conductive states at all times except for a brief period following the application of an end mark to their common cathodes.

Claim 39

The switching matrix of claim 31 wherein each of said bias means includes an impedance means connected between a bias supply source and the gate of the respective thyristor, and said bias supply source is selected to have an output voltage which is high relative to the voltage of said anode end mark, and wherein each of said control means includes means for maintaining the bias voltages applied to the gates of the non-conductive ones of its respective thyristors at substantially the output voltage of said bias supply source at all times except for a brief period following the end marking of their cathodes.

Claim 40

The switching matrix of claim 36 wherein said period is long relative to a predetermined turn-on time of said thyristors whereby any of said thyristors that have their anodes marked at the time their cathodes are marked switch into conduction regardless of the rate of change of their anode-cathode voltage.

Claim 41

The switching matrix of claim 37 wherein said thyristors, said impedance means, and said control means are included in the same integrated circuit.

Claim 42

The switching matrix of claim 31 wherein each of said control means includes a transistor which has a collector-emitter circuit connected in common to the bias means for its respective row of thyristors, and an input means coupled between the common cathodes of its row of thyristors and the base of said transistor for switching said transistor from a conductive state to a non-conductive state when said predetermined period elapses.

Claim 43

The switching matrix of claim 39 wherein the input means for each of said control means includes a Darlington pair in an emitter follower configuration whereby the loading of said matrix by sad control means is negligible.

Claim 44

The switching matrix of claim 39 wherein said bias means includes respective impedances connected between the gates of said thyristors and a bias supply source which is selected to have an output voltage which is high relative to the voltage of said anode end mark, and wherein each of said control means includes input means which maintain said transistor in a non-conductive state at all times except for a predetermined period following the application of a Mark to the common cathodes of its respective row of thyristors, whereby the non-conductive thyristors of each row are inhibited from switching into conduction by having their gates held at substantially the output voltage of said bias supply source all times except for said predetermined period.

Claim 45

The switching matrix of claim 41 wherein said impedances comprise respective field effect transistors having source drain circuits connected between said bias supply source and the gates of the respective thyristors and grounded bases, and wherein each of said control means further includes means connected in series with the collector-emitter circuit of the transistor therein for determining the bias voltage applied to the gates of the thyristors in its respective row of the matrix when the last mentioned transistor is in its conductive state.

Claim 46

The switching matrix of claim 42 wherein the input means of each of said control means includes a Darlington pair in an emitter follower configuration, whereby the loading of said matrix by said control means is negligible.

Claim 47

The switching matrix of claim 43 wherein said thyristors, said field effect transistors, and said control means are all included in the same integrated circuit.

Claim 48

An end mark controlled switching matrix comprising the combination of a plurality of three terminal, four layer thyristors each having an anode, a cathode, and a gate brought out from the layer adjacent said anode so as to be separated therefrom by an anode-gate junction, said thyristors being connected in rows and columns as crosspoints between inlets and outlets of said matrix with each row including a group of thyristors which have their cathodes connected in common and their anodes separately connected and each column including another group of thyristors which have their anodes connected in common and their cathodes separately connected; means for end marking the anodes of the thyristors in each column by applying a predetermined voltage thereto and for end marking the cathodes of the thyristors in each row by completing a low impedance return path to ground therefrom; a respective bias means coupled to the gate of each of said thyristors and isolated from the gate of each of said other thyristors for applying a bias voltage thereto which is independent of the bias voltage applied to the gates of the other thyristors, said bias means includes respective impedances connected between the gates of said thyristors and a bias supply source which is selected to have an output voltage which is high relative to the voltage of said anode end mark; and respective control means for the thyristors of each row, each of said control means includes a transistor which has a collector-emitter circuit connected in common to the gate bias means for its respective row of thyristors, and an input means coupled between the common cathodes of its row of thyristors and the base of said transistor for switching said transistor from a conductive state to a non-conductive state when a predetermined period has elapsed following the end marking of said cathodes and for maintaining said transistor in a non-conductive state at all times except for the said predetermined period following the application of a mark to the common cathodes of its respective row of thyristors, said input means including second and third transistors having parallel collector-emitter circuits connected to said bias supply source with the base of the second transistor connected to the common cathodes of the respective row of thyristors and the base of the third transistor connected to a fixed reference voltage means so that the second transistor is conductive and the third transistor is non-conductive when the voltage on said thyristor cathodes is above said fixed reference voltage, and the second transistor is non-conductive and the third transistor is conductive when the voltage on said thyristor cathodes is below said fixed reference voltage, and means responsive to conduction of said third transisTor for rendering the first transistor conductive when the voltage on said thyristor cathodes is below said fixed reference voltage, whereby said control means are effective to inhibit the non-conductive thyristors of each row from switching into conduction by having their gates held at substantially the output voltage of said bias supply source at all times except for said predetermined period.

Claim 49

An end mark controlled switching matrix comprising the combination of a plurality of three terminal, four layer thyristors each having an anode, a cathode, and a gate brought out from the layer adjacent said anode so as to be separated therefrom by an anode-gate junction, said thyristors being connected in rows and columns as crosspoints between inlets and outlets of said matrix with each row including a group of thyristors which have their cathodes connected in common and their anodes separately connected and each column including another group of thyristors which have their anodes connected in common and their cathodes separately connected; means for end marking the anodes of the thyristors in each column by applying a predetermined voltage thereto and for end marking the cathodes of the thyristors in each row by completing a low impedance return path to ground therefrom; a respective bias means coupled to the gate of each of said thyristors and isolated from the gate of each of said other thyristors for applying a bias voltage thereto which is independent of the bias voltage applied to the gates of the other thyristors, said bias means includes respective impedances connected between the gates of said thyristors and a bias supply source which is selected to have an output voltage which is high relative to the voltage of said anode end mark; and respective control means for the thyristors of each row, each of said control means includes a transistor which has a collector-emitter circuit connected in common to the gate bias means for its respective row of thyristors, and an input means coupled between the common cathodes of its row of thyristors and the base of said transistor for switching said transistor from a conductive state to a non-conductive state when a predetermined period has elapsed following the end marking of said cathodes and for maintaining said transistor in a non-conductive state at all times except for the said predetermined period following the application of a mark to the common cathodes of its respective row of thyristors, said input means including second and third transistors having parallel collector-emitter circuits connected to said bias supply source with the base of the second transistor connected to the common cathodes of the respective row of thyristors and the base of the third transistor connected to a fixed reference voltage means so that the second transistor is conductive and the third transistor is non-conductive when the voltage on said thyristor cathodes is above said fixed reference voltage, and the second transistor is non-conductive and the third transistor is conductive when the voltage on said thyristor cathodes is below said fixed reference voltage, and means responsive to conduction of said third transisTor for rendering the first transistor conductive when the voltage on said thyristor cathodes is below said fixed reference voltage, whereby said control means are effective to inhibit the non-conductive thyristors of each row from switching into conduction by having their gates held at substantially the output voltage of said bias supply source at all times except for said predetermined period.

Claim 50

The switching matrix of claim 45 wherein said means for rendering the first transistor conductive includes a fourth transistor having a collector-emitter circuit connected to the base of said first transistor and a base connected to the collector-emitter circuit of said third transistor for rendering said fourth and first transistors conductors in response to conduction of said third transistor.

Claim 51

The switching matrix of claim 45 which includes means for rendering said first transistor nonconductive at the end of said brief period following the end marking of the cathodes of said thyristors regardless of whether said third transistor is conductive at the end of said brief period.

Claim 52

The switching matrix of claim 47 wherein said means for rendering said first transistor nonconductive includes a fifth transistor having a collector-emitter circuit connected between the base and the collector-emitter circuit of said first transistor and a base connected to the collector-emitter circuit of said fourth transistor, whereby conduction of said fifth transistor renders said first transistor non-conductive, and a capacitor connected to the base of said fifth transistor for delaying the conduction of said fifth transistor until said capacitor accumulates a predetermined charge in response to the conduction of said fourth-transistor.

Claim 53

The switching matrix of claim 48 which includes a sixth transistor having a collector-emitter circuit connected to said capacitor and a base connected to a fixed reference voltage means for discharging said capacitor whenever said fourth transistor is non-conductive.

Claim 54

The switching matrix of claim 45 wherein said fixed reference voltage means includes circuit means connected to said bias supply source for furnishing said fixed reference voltage to a plurality of said input means coupled to a plurality of rows of thyristors in said matrix.

Claim 55

The switching matrix of claim 48 wherein the fixed reference voltage means connected to said sixth transistor and the fixed reference voltage means connected to said third transistor comprise a single circuit means connected to said bias supply source for furnishing fixed reference voltages of two different values to a plurality of said input means coupled to a plurality of rows of thyristors in said matrix.

Claim 56

The switching matrix of claim 45 wherein said thyristors, said impedance means, and said control means are all included in the same integrated circuit.