High speed driving circuit for producing two in-phase and two out-of-phase signals

Claim 2

A circuit for concurrently producing two in-phase signals and two out-of-phase signals comprising: first and second input terminals adapted to receive a binary input signal and its complement, respectively; first, second, third and fourth output terminals; first means coupled between said first input terminal and said first output terminal; second means coupled between said second input terminal and said second output terminal; said first and second means for producing at their respective output terminals a signal in-phase with the signals applied at their respective input terminals; third and fourth means, each of said third and fourth means having a conduction path and a control electrode for controlling the conductivity of said path; first coupling means coupled between said first input terminal and the control electrode of said fourth means for coupling to the latter the signal received at said first input terminal; second coupling means coupled between said second input terminal and the control electrode of said third means for coupling to the latter the signal received at said second input terminal; means connecting one end of the conduction path of said third means to said first output terminal and the other end of that conduction path to said third output terminal for providing a path for current to flow through said first and third means when said third means is enabled; and means connecting one end of the conduction path of said fourth means to said second output terminal and the other end of that conduction path to said fourth output terminal for providing a path for current to flow through said second and fourth means when said fourth means is enabled.

Claim 3

The circuit as claimed in claim 1, wherein each one of said means includes a transistor having a control electrode and first and second electrodes defining the ends of a conduction path and wherein each one of said first and second means includes a transistor connected in the voltage follower configuration, each voltage follower transistor being connected at its control electrode to an input terminal, at its first electrode to an output terminal, and at its second electrode to a point of fixed potential; wherein said third means includes a transistor direct current connected at its first electrode to said third output terminal and at its second electrode to said first output terminal and being coupled at its control electrode through said second coupling means to said second input terminal; and wherein said fourth means includes a transistor direct current connected at its first electrode to said fourth output terminal and at its second electrode to said second output terminal and being coupled at its control electrode through said first coupling means to said first input terminal.

Claim 4

The circuit as claimed in claim 2, wherein each one of said transistors is a bipolar transistor having a base, an emitter and a collector and wherein said base is said control electrode, said emitter is said first electrode and said collector is said second electrode; and wherein said first and second coupling means include level shift means.

Claim 5

The circuit as claimed in claim 3 further including a bridge circuit having first, second, third and fourth controllable conduction paths, each one of said controllable paths having a control electrode for controlling the conductivity of said path; each one of said control electrodes associated with a numbered path being connected to the correspondingly numbered one of said output terminals; the conduction of each of said controllable paths being controlled by the signal applied to its control electrode.

Claim 6

The circuit as claimed in claim 4, wherein said first and third paths of said bridge circuit are connected in series between two nodes and wherein said second and fourth paths of said bridge circuit are connected in series between said two nodes; further including a current source connected between said two nodes; and further including a load connected between the junction of said first and third paths and the junction of said second and fourth paths.

Claim 7

The circuit as claimed in claim 1, wherein each one of said first and second means includes two transistors connected in the emitter follower configuration, the first of said two transistors being connected at its base to an input terminal, at its emitter to the base of the second transistor, and the second transistor being connected at its emitter to an output terminal; wherein each one of said third and fourth means includes two transistors; wherein the first and second transistors of said first means are connected at their emitters to the collectors of the first and second transistors, respectively, of said third means; and wherein the first and second transistors of said second means are connected at their emitters to the collectors of the first and second transistors, respectively, of said fourth means.

Claim 8

The circuit as claimed in claim 1, further including fifth and sixth means, each one of said fifth and sixth means having a conduction path and a control electrode for controlling the conductivity of said conduction path; means coupling the control electrode of said fifth means to said first input terminal for applying to that control electrode the signal received at said first input terminal; means coupling the control electrode of said sixth means to said input terminal for applying to that control electrode the signal received at said second input terminal; means coupling the conduCtion path of said fifth means between said third output terminal and a point of fixed potential for conducting current through the conduction path of said fifth means between said third output terminal and said point of potential when said fifth means is enabled; and means coupling the conduction path of said sixth means between said fourth output terminal and said point of fixed potential for conducting current through the conduction path of said sixth means between said fourth output terminal and said point of potential, when said sixth means is enabled.

Claim 9

The circuit as claimed in claim 7 wherein said fifth and sixth means each include a transistor; wherein said transistor of said fifth means is connected at its collector to said third output terminal, at its emitter to said point of fixed potential and is coupled at its base to said first input terminal; and wherein said transistor of said sixth means is connected at its collector to said fourth output terminal, at its emitter to said point of fixed potential and is coupled at its base to said second input terminal.

Claim 10

The combination comprising: two pairs of two transistors, each transistor having a control electrode and first and second electrodes defining the ends of a conduction path; each pair including a first transistor connected at its first electrode to the second electrode of the second transistor of the pair for providing a current path for the conduction path of the latter; first and second terminals for the application thereto of a signal and its complement, respectively; four output terminals; means connecting each transistor at its first electrode to a different one of said four output terminals; means coupling the control electrode of the first transistor of one pair to said first terminal and first level shift means coupling the control electrode of the second transistor of the other pair to said first terminal for producing at the first electrodes of the first transistor of one pair and the second transistor of said other pair a signal in phase with that applied at said first terminal; and means coupling the control electrode of the first transistor of the other pair to said second terminal and second level shift means coupling the control electrode of the second transistor of said one pair to said second terminal for producing at the first electrodes of the first transistor of the other pair and the second transistor of said one pair a signal in phase with the signal applied at said second terminal.

Claim 11

The combination comprising: two pairs of two transistors, each transistor having a control electrode and first and second electrodes defining the ends of a conduction path; each pair including a first transistor connected at its first electrode to the second electrode of the second transistor of the pair for providing a current path for the conduction path of the latter; first and second terminals for the application thereto of a signal and its complement, respectively; four output terminals; means connecting each transistor at its first electrode to a different one of said four output terminals; means coupling the control electrode of the first transistor of one pair to said first terminal and first level shift means coupling the control electrode of the second transistor of the other pair to said first terminal for producing at the first electrodes of the first transistor of one pair and the second transistor of said other pair a signal in phase with that applied at said first terminal; and means coupling the control electrode of the first transistor of the other pair to said second terminal and second level shift means coupling the control electrode of the second transistor of said one pair to said second terminal for producing at the first electrodes of the first transistor of the other pair and the second transistor of said one pair a signal in phase with the signal applied at said second terminal.

Claim 12

The combination as claimed in claim 9, wherein each one of said transistors is a bipolar transistor having a base, an emitter and a collector electrode, and wherein said base electrode is said control electrode, said emitter electrode is said first electrode and said collector electrode is said second electrode.

Claim 13

In combination with a bridge network having four controllable paths, each controllable path having a conduction path and a control electrode for controlling the conduction of the path, first and second ones of said controllable paths being connected between a common first terminal and second and third terminals, respectively, and third and fourth ones of said paths being connected between a common fourth terminal and said second and third terminals, respectively, a driving circuit comprising: first and second input points adapted to receive a first signal and its complement, respectively; first means coupled between said first input point and the control electrode of said first controllable path for providing a switch-on current to said first controllable path in response to a turn-on signal at said first input point; second means coupled between said second input point and the control electrode of said second controllable path for providing a switch-on current to said second controllable path in response to a turn-on signal at said second input point; third and fourth means, each having a conduction path and a control eLectrode; means coupling the control electrode of said third means to said first input point; means connecting the conduction path of said third means between the control electrodes of said second and fourth controllable bridge paths for providing a switch-on current to said fourth controllable path which flows in said second means and flows in a direction to turn on said fourth controllable path and turn off said second controllable path in response to a turn-on signal at said first input point; means coupling the control electrode of said fourth means to said second input point; and means connecting the conduction path of said fourth means between the control electrodes of said first and third controllable bridge paths for providing a switch-on current to said third controllable path which flows in said first means and flows in a direction to turn on said third controllable path and turn off said first controllable path in response to a turn-on signal at said second input point.

Claim 14

In combination with a bridge network having four controllable paths, each controllable path having a conduction path and a control electrode for controlling the conduction of the path, first and second ones of said controllable paths being connected between a common first terminal and second and third terminals, respectively, and third and fourth ones of said paths being connected between a common fourth terminal and said second and third terminals, respectively, a driving circuit comprising: first and second input points adapted to receive a first signal and its complement, respectively; first means coupled between said first input point and the control electrode of said first controllable path for providing a switch-on current to said first controllable path in response to a turn-on signal at said first input point; second means coupled between said second input point and the control electrode of said second controllable path for providing a switch-on current to said second controllable path in response to a turn-on signal at said second input point; third and fourth means, each having a conduction path and a control eLectrode; means coupling the control electrode of said third means to said first input point; means connecting the conduction path of said third means between the control electrodes of said second and fourth controllable bridge paths for providing a switch-on current to said fourth controllable path which flows in said second means and flows in a direction to turn on said fourth controllable path and turn off said second controllable path in response to a turn-on signal at said first input point; means coupling the control electrode of said fourth means to said second input point; and means connecting the conduction path of said fourth means between the control electrodes of said first and third controllable bridge paths for providing a switch-on current to said third controllable path which flows in said first means and flows in a direction to turn on said third controllable path and turn off said first controllable path in response to a turn-on signal at said second input point.

Claim 15

A circuit for concurrently producing two in-phase signals and two out-of-phase signals comprising: first and second input terminals adapted to receive a binary input signal and its complement, respectively; first (Q3a), second (Q3b), third (Q5b) and fourth (Q5a) transistors, each transistor having a base, an emitter and a collector; means connecting the base of said first transistor (Q3a) to said first input terminal (A) and means connecting the base of said second transistor (Q3b) to said second input terminal (B); means connecting the collector of said third transistor (Q5b) and means connecting the base of said fourth transistor (Q5a) to the emitter of said first transistor; means connecting the collector of said fourth transistor (Q5a) and means connecting the base of said third transistor (Q5b) to the emitter of said second transistor (Q3b); and output means connected to the emitters of said transistors for deriving signals from the emitters of said first and fourth transistors which are in-phase with each other and out-of-phase with the signals derived from the emitters of said second and third transistors.

Claim 16

A circuit for concurrently producing two in-phase signals and two out-of-phase signals comprising: first and second input terminals adapted to receive a binary input signal and its complement, respectively; first (Q3a), second (Q3b), third (Q5b) and fourth (Q5a) transistors, each transistor having a base, an emitter and a collector; means connecting the base of said first transistor (Q3a) to said first input terminal (A) and means connecting the base of said second transistor (Q3b) to said second input terminal (B); means connecting the collector of said third transistor (Q5b) and means connecting the base of said fourth transistor (Q5a) to the emitter of said first transistor; means connecting the collector of said fourth transistor (Q5a) and means connecting the base of said third transistor (Q5b) to the emitter of said second transistor (Q3b); and output means connected to the emitters of said transistors for deriving signals from the emitters of said first and fourth transistors which are in-phase with each other and out-of-phase with the signals derived from the emitters of said second and third transistors.

Claim 17

The combination as claimed in claim 12 further including fifth and sixth transistors, each transistor having a base, an emitter and a collector; means connecting the collector of said fifth transistor (Q7a) and the base of said sixth transistor (Q7b) to the emitter of said third transistor (Q5b); and means connecting the collector of said sixth transistor (Q7b) and means connecting the base of said fifth transistor (Q7a) to the emitter of said fourth transistor.

Claim 18

The combination as claimed in claim 12 wherein said output means includes, first, second, third and fourth output terminals; and further includes: a fifth transistor (Q31a) having its base-to-emitter path connected between the emitter of said first transistor (Q3a) and said first output terminal; a sixth transistor (Q31b) having its base-to-emitter connected between the emitter of said second transistor (Q3b) and said second output terminal, a seventh transistor (Q51b) having its base-to-emitter path connected between the emitter of said third transistor (Q5b) and said third output terminal and an eighth transistor (Q51a) having its base-to-emitter connected between the emitter of said fourth transistor (Q5a) and said fourth output terminal; and further including means for connecting the collector of said seventh transistor (Q51b) to the emitter of said fifth transistor (Q31a) and the collector of said eighth transistor (Q51a) to the emitter of said sixth transistor (Q31b).