Sensitive pulse threshold detector

Claim 2

A signal detector comprising: first means having input means which comprise first and second input terminals for providing an output voltage at a level which is a function of the voltage difference between said input terminals; a gate terminal at which a gate pulse of a selected duration is applicable; control means coupled to said first means and to said gate terminal for applying during the absence of a gate pulse a prebias voltage to said input means as a function of the output voltage of said first means to maintain the output voltage substantially constant at a selected level and for applying said prebias voltage to said input means during the duration of said gate pulse at the same level at which the prebias voltage was applied at the start of said gate pulse; second means for applying a bias voltage to said input means during said gate pulse period; and third means responsive to an input signal for applying an input voltage, which is related to the input signal amplitude, to said input means, whereby the output voltage of said first means deviates in a selected direction from said selected level by at least a selected first factor only when the amplitude of said input voltage exceeds the bias voltage amplitude by a selected second factor, which is independent of the amplitude of the prebias voltage applied to said input meanS during the gate pulse duration.

Claim 3

A signal detector as recited in claim 1 wherein said control means include voltage storage means for storing a voltage at an amplitude related to the amplitude of the output voltage of said first means during the absence of said gate pulse and for retaining the voltage stored therein related to the amplitude of the output voltage of said first means just prior to said gate pulse during the entire gate pulse duration; and means coupled to said voltage storage means for controlling the prebias voltage amplitude as a function of the voltage amplitude stored in said voltage storage means.

Claim 4

A signal detector as recited in claim 2 wherein said second means include means for maintaining the bias voltage amplitude constant during the gate pulse duration.

Claim 5

A signal detector as recited in claim 2 wherein said second means comprise means for varying the bias voltage amplitude during the gate pulse duration.

Claim 6

A signal detector comprising: am amplifier of the type having first and second input terminals defining amplifier input means and an output terminal for providing at said output terminal an output voltage at an amplitude which is a function of the amplitude difference of the voltages at said first and second input terminals, said output voltage amplitude varying linearly between a first amplitude and a second lower amplitude; gate means including a gate terminal at which a gate pulse of a selected duration is applied for applying a bias voltage, definable as VB, to said amplifier input means during said gate pulse duration; circuit input means including a circuit input terminal at which an input signal is applied during said gate pulse period for applying an input voltage, definable as VI, to said amplifier input means, the amplitude of VI being a function of the input signal amplitude; and control means coupled to said amplifier and to said gate means for applying during the absence of a gate pulse a prebias voltage to said amplifier input means at an amplitude which is a function of the amplitude of the amplifier output voltage so as to maintain the output voltage of said amplifier substantially constant at a selected amplitude in its linear region, and for applying during the gate pulse period said prebias voltage to said amplifier input means at a constant amplitude equal to the prebias voltage amplitude applied to said amplifier input means at the start of said gate pulse period, whereby when said bias voltage VB and said input voltage VI are applied to said amplifier input means, the output voltage amplitude deviates in a given direction from said selected amplitude by more than a selected first factor only when the amplitude difference between VB and VI is not less than a known second factor.

Claim 7

A signal detector comprising: am amplifier of the type having first and second input terminals defining amplifier input means and an output terminal for providing at said output terminal an output voltage at an amplitude which is a function of the amplitude difference of the voltages at said first and second input terminals, said output voltage amplitude varying linearly between a first amplitude and a second lower amplitude; gate means including a gate terminal at which a gate pulse of a selected duration is applied for applying a bias voltage, definable as VB, to said amplifier input means during said gate pulse duration; circuit input means including a circuit input terminal at which an input signal is applied during said gate pulse period for applying an input voltage, definable as VI, to said amplifier input means, the amplitude of VI being a function of the input signal amplitude; and control means coupled to said amplifier and to said gate means for applying during the absence of a gate pulse a prebias voltage to said amplifier input means at an amplitude which is a function of the amplitude of the amplifier output voltage so as to maintain the output voltage of said amplifier substantially constant at a selected amplitude in its linear region, and for applying during the gate pulse period said prebias voltage to said amplifier input means at a constant amplitude equal to the prebias voltage amplitude applied to said amplifier input means at the start of said gate pulse period, whereby when said bias voltage VB and said input voltage VI are applied to said amplifier input means, the output voltage amplitude deviates in a given direction from said selected amplitude by more than a selected first factor only when the amplitude difference between VB and VI is not less than a known second factor.

Claim 8

A signal detector as recited in claim 5 wherein said gate means include means for maintaining said bias voltage amplitude constant during the gate pulse duration.

Claim 9

A signal detector as recited in claim 5 wherein said gate means include means for varying the bias voltage amplitude during the gate pulse duration.

Claim 10

A signal detector as recited in claim 5 wherein said amplifier with said first and second input terminals being the inverting and non-inverting input terminals of said operational amplifier, which is characterized by a varying offset voltage representing the voltage difference between said input terminals required to maintain the output voltage substantially constant at said selected level under varying operating conditions of said operational amplifier, and said control means include means for automatically applying said prebias voltage to said input means at an amplitude corresponding to the amplitude of said offset voltage as a function of the output voltage amplitude so as to maintain said output voltage at said selected amplitude during the absence of said gate pulse.

Claim 11

A signal detector as recited in claim 8 wherein said gate means include means for maintaining the amplitude of said bias voltage substantially constant during said gate pulse duration.

Claim 12

A signal detector as recited in claim 8 wherein said gate means include means for varying the bias voltage amplitude during the gate pulse duration.

Claim 13

In combination with an amplifier of the type including a pair of input terminals, defining amplifier input means, and an output terminal at which an output voltage is produced which is a function of the voltage difference between said input terminals, said output voltage varying linearly in a linear region between an upper saturation level and a lower saturation level, said amplifier being characterized by a varying offset voltage definable as Voff which represents the required voltage difference between said input terminals needed to maintain the output voltage at the same level in its linear region under different operating conditions, the arrangement comprising: gate means including a gate terminal at which a gate pulse of a selected duration is applied for applying a bias voltage definable as VB to said amplifier input means; control means coupled to said amplifier and to said gate means for providing a variable prebias voltage to said amplifier input means as a function of the amplifier output voltage during the absence of said gate pulse so as to maintain said output voltage at a selected substantially constant level in its linear region, and for applying said prebias voltage to said amplifier input means during the gate pulse duration at a level which is constant and equal to the prebias voltage at the start of said gate pulse; and circuit means including a circuit input terminal at which an input signal is applied during the gate pulse duration for applying an input voltage definable as VI to said amplifier input means, whereby during the gate pulse duration, the deviation of the output voltage from said selected substantially constant level is a function of the difference between VB and VI and is substantially independent of said offset voltage.

Claim 14

In combination with an amplifier of the type including a pair of input terminals, defining amplifier input means, and an output terminal at which an output voltage is produced which is a function of the voltage difference between said input terminals, said output voltage varying linearly in a linear region between an upper saturation level and a lower saturation level, said amplifier being characterized by a varying offset voltage definable as Voff which represents the required voltage difference between said input terminals needed to maintain the output voltage at the same level in its linear region under different operating conditions, the arrangement comprising: gate means including a gate terminal at which a gate pulse of a selected duration is applied for applying a bias voltage definable as VB to said amplifier input means; control means coupled to said amplifier and to said gate means for providing a variable prebias voltage to said amplifier input means as a function of the amplifier output voltage during the absence of said gate pulse so as to maintain said output voltage at a selected substantially constant level in its linear region, and for applying said prebias voltage to said amplifier input means during the gate pulse duration at a level which is constant and equal to the prebias voltage at the start of said gate pulse; and circuit means including a circuit input terminal at which an input signal is applied during the gate pulse duration for applying an input voltage definable as VI to said amplifier input means, whereby during the gate pulse duration, the deviation of the output voltage from said selected substantially constant level is a function of the difference between VB and VI and is substantially independent of said offset voltage.

Claim 15

The combination as recited in claim 11 wherein said gate means comprise means for applying said bias voltage VB at a constant amplitude during the gate pulse duration.

Claim 16

The combination as recited in claim 11 wherein said control means include voltage storage means and connecting means for connecting said voltage storage means to the amplifier output terminal during the absence of said gate pulse, and for decoupling said voltage storage means from said output terminal during the gate pulse duration, whereby in the absence of said gate pulse, said voltage storage means stores the output voltage and during the gate pulse duration said voltage storage means retains the last voltage stored therein, and means for applying said prebias voltage to said amplifier input means as a function of the voltage stored in said voltage storing means.

Claim 17

The combination as recited in claim 13 wherein said arrangement includes means for applying a first reference voltage to said first input terminal during at least the absence of said gate pulse, and means for controlling the voltage at said second terminal with respect to said first reference voltage as a function of the voltage stored in said voltage storing means so that the output voltage in the absence of said gate pulse is at substantially said selected level.

Claim 18

The combination as recited in claim 14 wherein said first and second input terminals are the non-inverting and inverting input terminals of said amplifier, said control means including a source of a second reference voltage, a first resistor connected between said second reference voltage and said second input terminal and a second resistor connected between said second input terminal and means at which a voltage is applied which is substantially equal to the voltage stored in said voltage storing means, whereby an increase in the voltage in said voltage storing means increases the voltage at said second inverting input terminal.

Claim 19

The combination as recited in claim 15 wherein said gate means include means for varying the resistance between said second reference voltage source and said second input terminal during the gate pulse period to thereby change the voltage thereat from the voltage applied thereto prior to the gate pulse by the bias voltage VB.

Claim 20

In combination with a regenerative voltage circuit of the type including first and second input terminals defining input means and an output terminal at which an output voltage is provided at a level which is a function of the voltage difference between said output terminals, said output voltage level being switchable from a first level to a second level when said voltage difference exceeds a value defining a first trigger value of said circuit, with said output voltage being switchable from said second level to said first level when the voltage difference is less than a value defining a second trigger value of said circuit, which differs from said first trigger value, an arrangement comprising: a gate terminal at which a gate pulse of a selected duration is applied; control means coupled to said circuit and responsive to said gate pulse for automatically adjusting said voltage difference to equal said first trigger value so as to maintain the output voltage of said circuit at substantially said first level in the absence of said gate pulse and for biasing said input means by a bias voltage definable as VB during the gate pulse duration so as to vary the voltage difference from said trigger value by VB in a direction which maintains said output voltage at said first level, said control means including means for resetting said circuit in said first level when said output voltage is at said second level; and means including an input terminal at which an input signal is applied during the gate pulse duration coupled to said circuit for varying the voltage difference between said first and second input terminals in a direction toward said first trigger value by an input voltage, definable as VI, which is related to the input signal amplitude, so that said voltage difference exceeds said first trigger value and said output voltage switches from said first level to said second level only when the amplitude of VI exceeds the amplitude of VB.

Claim 21

In combination with a regenerative voltage circuit of the type including first and second input terminals defining input means and an output terminal at which an output voltage is provided at a level which is a function of the voltage difference between said output terminals, said output voltage level being switchable from a first level to a second level when said voltage difference exceeds a value defining a first trigger value of said circuit, with said output voltage being switchable from said second level to said first level when the voltage difference is less than a value defining a second trigger value of said circuit, which differs from said first trigger value, an arrangement comprising: a gate terminal at which a gate pulse of a selected duration is applied; control means coupled to said circuit and responsive to said gate pulse for automatically adjusting said voltage difference to equal said first trigger value so as to maintain the output voltage of said circuit at substantially said first level in the absence of said gate pulse and for biasing said input means by a bias voltage definable as VB during the gate pulse duration so as to vary the voltage difference from said trigger value by VB in a direction which maintains said output voltage at said first level, said control means including means for resetting said circuit in said first level when said output voltage is at said second level; and means including an input terminal at which an input signal is applied during the gate pulse duration coupled to said circuit for varying the voltage difference between said first and second input terminals in a direction toward said first trigger value by an input voltage, definable as VI, which is related to the input signal amplitude, so that said voltage difference exceeds said first trigger value and said output voltage switches from said first level to said second level only when the amplitude of VI exceeds the amplitude of VB.

Claim 22

The arrangement as recited in claim 17 wherein said control means include means for maintaining said bias voltage constant during the gate pulse duration.

Claim 23

The arrangement as recited in claim 17 wherein said control means include means for varying said bias voltage during said gate pulse duration.

Claim 24

In combination with an operational amplifier of the type including a pair of input terminals, defining amplifier input means, and an output terminal at which an output voltage is produced which is a function of the input voltage difference between said input terminals, said output voltage varying linearly in a linear region between an upper saturation level and a lower saturation level, said amplifier being characterized by a varying offset voltage definable as Voff which represents the required voltage difference between said input terminals needed to maintain the output voltage at the same level in its linear region under different operating conditions, the arrangement comprising: a gate terminal at which a gate pulse of a selected duration is applied; control means coupled to said amplifier and responsive to said gate pulse for automatically controlling said input voltage difference during the absence of said gate pulse so that the output voltage is substantially constant at a first selected level in said linear region spaced apart from a second selected level, and for varying the input voltage difference during the gate pulse duration by a bias voltage definable as VB, from the input voltage difference aT the start of said gate pulse so that the output voltage level changes from said first selected level to a third level in a direction away from said second selected level; and means coupled to said circuit and including an input terminal at which an input signal is applied during the gate pulse duration for applying an input voltage to said circuit input means, said input voltage definable as VI being related to the amplitude of said input signal, said input voltage varying the input voltage difference in a direction so that said output voltage varies from said third level toward said first level, exceeding said second level only when the amplitude of said input voltage VI exceeds the amplitude of the bias voltage VB by a fixed factor which is independent of said off-set voltage.

Claim 25

In combination with an operational amplifier of the type including a pair of input terminals, defining amplifier input means, and an output terminal at which an output voltage is produced which is a function of the input voltage difference between said input terminals, said output voltage varying linearly in a linear region between an upper saturation level and a lower saturation level, said amplifier being characterized by a varying offset voltage definable as Voff which represents the required voltage difference between said input terminals needed to maintain the output voltage at the same level in its linear region under different operating conditions, the arrangement comprising: a gate terminal at which a gate pulse of a selected duration is applied; control means coupled to said amplifier and responsive to said gate pulse for automatically controlling said input voltage difference during the absence of said gate pulse so that the output voltage is substantially constant at a first selected level in said linear region spaced apart from a second selected level, and for varying the input voltage difference during the gate pulse duration by a bias voltage definable as VB, from the input voltage difference aT the start of said gate pulse so that the output voltage level changes from said first selected level to a third level in a direction away from said second selected level; and means coupled to said circuit and including an input terminal at which an input signal is applied during the gate pulse duration for applying an input voltage to said circuit input means, said input voltage definable as VI being related to the amplitude of said input signal, said input voltage varying the input voltage difference in a direction so that said output voltage varies from said third level toward said first level, exceeding said second level only when the amplitude of said input voltage VI exceeds the amplitude of the bias voltage VB by a fixed factor which is independent of said off-set voltage.

Claim 26

In combination with a regenerative voltage circuit of the type including a pair of input terminals defining input means and an output terminal, the output voltage at said output terminal being switchable between said first and second levels, with the output voltage switching from said first to said second level only when the voltage difference between said input terminals deviates in a first direction from a first trigger value and said output voltage switches from said second level to said first level when the voltage difference deviates in a second direction from a second trigger value, which differs from said first trigger value, the arrangement comprising: a gate terminal at which a gate pulse of a selected duration is applied; control means coupled to said regenerative voltage circuit and to said gate terminal for applying to the input means of said circuit a prebias voltage to control said voltage difference to equal a selected one of said trigger values during the absence of a gate pulse and for maintaining said prebias voltage constant at the level applied just prior to the gate pulse during the gate pulse duration; bias means responsive to said gate pulse for applying a bias voltage to said input means during the gate pulse duration so as to bias said voltage difference away from said selected trigger value; and circuit means responsive to an input signal and coupled to said input means for applying to said input means an input voltage at an amplitude related to the input signal amplitude to bias said voltage difference toward said selected trigger value thereby said output voltage changes from its level prior to the gate pulse to the other level only if the amplitude of said input voltage exceeds the bias voltage amplitude.

Claim 27

In combination with a regenerative voltage circuit of the type including a pair of input terminals defining input means and an output terminal, the output voltage at said output terminal being switchable between said first and second levels, with the output voltage switching from said first to said second level only when the voltage difference between said input terminals deviates in a first direction from a first trigger value and said output voltage switches from said second level to said first level when the voltage difference deviates in a second direction from a second trigger value, which differs from said first trigger value, the arrangement comprising: a gate terminal at which a gate pulse of a selected duration is applied; control means coupled to said regenerative voltage circuit and to said gate terminal for applying to the input means of said circuit a prebias voltage to control said voltage difference to equal a selected one of said trigger values during the absence of a gate pulse and for maintaining said prebias voltage constant at the level applied just prior to the gate pulse during the gate pulse duration; bias means responsive to said gate pulse for applying a bias voltage to said input means during the gate pulse duration so as to bias said voltage difference away from said selected trigger value; and circuit means responsive to an input signal and coupled to said input means for applying to said input means an input voltage at an amplitude related to the input signal amplitude to bias said voltage difference toward said selected trigger value thereby said output voltage changes from its level prior to the gate pulse to the other level only if the amplitude of said input voltage exceeds the bias voltage amplitude.

Claim 28

The arrangement as recited in claim 21 wherein said bias means include means for maintaining said bias voltage constant during said gate pulse duration.

Claim 29

The arrangement as recited in claim 21 wherein said bias means include means for varying the bias voltage during said gate pulse duration.

Claim 30

A signal detector responsive to applied input signals and gate pulses for providing an output signal which is indicative of the simultaneous occurrence of an input signal that exceeds a threshold value and a gate pulse, said detector having: a tunnel diode which is switchable from a low to a high voltage state in response to a current which exceeds a first value flowing therethrough and which is switchable from said high to said low voltage state when the current through the tunnel diode is less than a second value; control means for providing during the gate pulse intervals a pre-bias current substantially equal to said first value; bias means for reducing during the gate pulse intervals the current flowing through said tunnel diode by an amount which is a function of said threshold value; means for coupling said input signals to said tunnel diode during the gate pulse intervals; output means for producing an output signal when said tunnel diode is in its high voltage state during a gate pulse interval; and wherein the improvement comprises said control means including means for sensing when said tunnel diode is in its high voltage state; means for reducing the current through said tunnel diode below said second value for a first time interval following each time the high voltage state of said tunnel diode is sensed; means for producing a control signal, having a duration of a second time interval, following each time a high voltage state of said tunnel diode is sensed, with said second time interval being longer than said first time interval; integrator means for providing during the interval between gate pulses a pre-bias current which increases substantially linearly during the absence of said control signal and which decreases substantially linearly during the presence of said control signal and for providing a pre-bias current during the gate pulse intervals which is substantially equal to the value of the pre-bias current at the start of each respective gate pulse; and means for applying said pre-bias current to said tunnel diode.

Claim 31

A signal detector responsive to applied input signals and gate pulses for providing an output signal which is indicative of the simultaneous occurrence of an input signal that exceeds a threshold value and a gate pulse, said detector having: a tunnel diode which is switchable from a low to a high voltage state in response to a current which exceeds a first value flowing therethrough and which is switchable from said high to said low voltage state when the current through the tunnel diode is less than a second value; control means for providing during the gate pulse intervals a pre-bias current substantially equal to said first value; bias means for reducing during the gate pulse intervals the current flowing through said tunnel diode by an amount which is a function of said threshold value; means for coupling said input signals to said tunnel diode during the gate pulse intervals; output means for producing an output signal when said tunnel diode is in its high voltage state during a gate pulse interval; and wherein the improvement comprises said control means including means for sensing when said tunnel diode is in its high voltage state; means for reducing the current through said tunnel diode below said second value for a first time interval following each time the high voltage state of said tunnel diode is sensed; means for producing a control signal, having a duration of a second time interval, following each time a high voltage state of said tunnel diode is sensed, with said second time interval being longer than said first time interval; integrator means for providing during the interval between gate pulses a pre-bias current which increases substantially linearly during the absence of said control signal and which decreases substantially linearly during the presence of said control signal and for providing a pre-bias current during the gate pulse intervals which is substantially equal to the value of the pre-bias current at the start of each respective gate pulse; and means for applying said pre-bias current to said tunnel diode.

Claim 32

The signal detector of claim 24 wherein said bias means includes means for varying, during the gate pulse interval, the current flowing through said tunnel diode.