US3823348A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Monolithic integrated structure including fabrication and package therefor
Assignee: International Business Machines Corp
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Filing: 1970-04-16
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Granted: 1974-07-09
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Expires: 1990-04-16
Abstract
Abstract A monolithic integrated semiconductor structure is described that has a plurality of functionally isolated individual cells that are electrically interconnected. Each of the cells is an object or mirror image cell that is vertically, horizontally and diagonally displaced from the object cell. The plurality of cells provide a memory array with electrical components of each memory cell composed of active and passive semiconductor devices. Other important aspects of the structure include underpass connections and active devices in a common portion of the structure which are electrically interconnected at the same node potential by means of a highly doped buried region within the common portion of the structure. In particular, a sophisticated packaging scheme for containing such a highly complex array of memory cells is disclosed.
Inventors
- 👤 P Castrucci
- 👤 R Henle
- 👤 B Agusta
- 👤 P Bardell
- 👤 R Pecoraro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:30
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; H03K3/288
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
131 words
A monolithic integrated semiconductor structure comprising, in combination, a plurality of functionally isolated individual cells electrically interconnected, each of said cells comprising active and passive devices, one of said active devices comprises a diode and a transistor, said diode and transistor being located in a common portion of said monolithic semiconductor structure which is isolated from other said active and passive devices, said diode and transistor in said common portion of the structure being electrically interconnected at the same node potential by means of a highly doped buried region within said common portion of the structure, each of said cells is provided with external terminal connection regions electrically interconnected to said cells, each of said external connection regions comprising layers of chrome, copper, and gold electrically connected to a lead-tin pad.
Claim 2
Dependent Claim
131 words
A monolithic integrated semiconductor structure comprising, in combination, a plurality of functionally isolated individual cells electrically interconnected, each of said cells comprising active and passive devices, one of said active devices comprises a diode and a transistor, said diode and transistor being located in a common portion of said monolithic semiconductor structure which is isolated from other said active and passive devices, said diode and transistor in said common portion of the structure being electrically interconnected at the same node potential by means of a highly doped buried region within said common portion of the structure, each of said cells is provided with external terminal connection regions electrically interconnected to said cells, each of said external connection regions comprising layers of chrome, copper, and gold electrically connected to a lead-tin pad.
Claim 3
Dependent Claim
29 words
A monolithic integrated semiconductor structure in accordance with claim 1, in which an aluminum land pattern is provided for electrically interconnecting the selected terminal connection regiOns to each cell.
Claim 4
Dependent Claim
161 words
A package for monolithic integrated memory arrays comprising, in combination: a dielectric substrate; a conductive land pattern formed on a surface of said dielectric substrate including terminal end portions; a plurality of pins penetrating said dielectric substrate and connected to selected terminal end portions; at least two monolithic integrated memory array chips spaced from the surface of said dielectric substrate and interconnected to said lands; each said monolithic integrated memory array chips being formed on a monocrystalline semiconductor substrate having terminal pads located about the peripheral portion of said monocrystalline semiconductor substrate, the terminal pads being formed in sets of substantially parallel lines thereby defining an area in said monocrystalline semiconductor substrate, each said area including a plurality of functionally isolated memory cells, each said cells having an electrical connection to a terminal pad each terminal pad comprising layers of chrome, copper and gold electrically connected to one of said conductive land patterns formed on the surface of said dielectric substrate.
Claim 5
Dependent Claim
161 words
A package for monolithic integrated memory arrays comprising, in combination: a dielectric substrate; a conductive land pattern formed on a surface of said dielectric substrate including terminal end portions; a plurality of pins penetrating said dielectric substrate and connected to selected terminal end portions; at least two monolithic integrated memory array chips spaced from the surface of said dielectric substrate and interconnected to said lands; each said monolithic integrated memory array chips being formed on a monocrystalline semiconductor substrate having terminal pads located about the peripheral portion of said monocrystalline semiconductor substrate, the terminal pads being formed in sets of substantially parallel lines thereby defining an area in said monocrystalline semiconductor substrate, each said area including a plurality of functionally isolated memory cells, each said cells having an electrical connection to a terminal pad each terminal pad comprising layers of chrome, copper and gold electrically connected to one of said conductive land patterns formed on the surface of said dielectric substrate.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-07-08 | 1978-01-07 | 1978-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-07-08 | 1982-01-07 | 1982-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-07-08 | 1986-01-07 | 1986-07-09 | $7700.00 | Window Closed / Lapsed |