Pulse train modification circuit

Claim 2

A pulse train modification circuit, said circuit comprising: first means to supply discrete input pulses; second means connected from said first means to supply discrete first output pulses in synchronism with said input pulses; a storage register; third means to vary the contents of said register in direct proportion to the magnitude of a predetermined variable; and fourth means connected from said first means and from said register to insert a predetermined number of discrete second output pulses in between corresponding immediately adjacent pairs of said first output pulses, said predetermined number being directly proportional to the number stored in said register.

Claim 3

The invention as defined in claim 1, including utilization means connected to receive said first and second output pulses in a single pulse train.

Claim 4

The invention as defined in claim 2, wherein said first means includes a turbine flowmeter, said third means including fifth means to provide a D.C. voltage directly proportional to the temperature of the fluid flowing through said flowmeter and sixth means connected from said fifth means to said register to vary the contents of said register in direct proportion to the amplitude of said D.C. voltage.

Claim 5

The invention as defined in claim 3, wherein said utilization means includes a pulse counter connected from said fourth means and an indicator connected from said counter, said indicator indicating visually the magnitude of the count in said counter.

Claim 6

The invention as defined in claim 2, wherein said utilization means includes a pulse counter connected from said fourth means and an indicator connected from said counter, said indicator indicating visually the magnitude of the count in said counter.

Claim 7

The invention as defined in claim 1, wherein said second means includes an inverter connected from said first means, a first binary digital pulse countEr connected from said inverter, said first counter having n flip-flops, a first OR gate, a differentiator connected from the 1 output of each first counter flip-flop to said first OR gate, a logic circuit connected from said inverter to said first counter flip-flops, said logic circuit being adapted to reset said flip-flops every mth input pulse thereto where n and m are positive integers, m being not less than 2, a second binary digital pulse counter having first, second, third ... pth flip-flops, a second OR gate, a first auxiliary differentiator connected from said first means to said second OR gate, a second auxiliary differentiator connected from said inverter to said second OR gate, said second counter having a logic circuit connected from said second OR gate to said second counter flip-flops, first, second, third ... pth AND gates, first, second, third ... pth differentiators connected from the 1 outputs of said first, second, third ... pth second counter flip-flops, respectively, to the inputs of said first, second, third ... pth AND gates, respectively, said first, second, third ... pth second counter flip-flops producing pulses at the 1 outputs thereof at pulse repetition frequencies f, f/2, f/4, ... f/p, respectively, where f is 2 times the pulse repetition frequency of the input pulses supplied by said first means, an analog-to-digital converter including a control circuit and a storage register connected therefrom, means to supply a D.C. voltage to said control circuit of an amplitude variable in direct proportion to the magnitude of a predetermined variable, an auxiliary storage register, means connected from said second auxiliary differentiator and said converter register to said auxiliary register to enter the contents of said converter register into said storage register when a pulse appears at the output of said second auxiliary differentiator, said auxiliary register having first, second, third ... pth flip-flops with their 1 outputs connected to the inputs of said first, second, third ... pth AND gates, respectively, said first, second, third ... pth auxiliary register flip-flops carrying binary digits which are the most, second most, third most ... least significant of the number entered in said auxiliary register, a divide-by-q divider, a third OR gate connected from the output of said AND gates to the input of said divider, an auxiliary flip-flop having set and reset inputs, and a 0 output, a differentiator connected from the output of said divider to the set input of said auxiliary flip-flop, said auxiliary flip-flop reset input being connected from the output of said first auxiliary differentiator, and a third auxiliary differentiator connected from said auxiliary flip-flop 0 output to the input of said first OR gate.

Claim 8

The invention as defined in claim 6, wherein n 4, m 10 and q 10.

Claim 9

The invention as defined in claim 7, wherein p 8.

Claim 10

The invention as defined in claim 1, wherein said third means includes a Kelvin-Varley function generator to produce a signal directly proportional to specific gravity in response to a manual setting equal to G, where G 141.5/S - 131.5 where S is specific gravity.

Claim 11

Apparatus for generating a serial group of pulses wherein the number of pulses in a group is equal to a known variable digital number, said apparatus comprising: a binary digital pulse counter including a logic circuit and at least first and second flip-flops connected therefrom; means to supply input pulses to said logic circuit at a pulse repetition frequency 2f; at least first and second AND gates each having first and second inputs and an output, said counter first and second flip-flops having first and sEcond 1 outputs, respectively, first means connecting said first counter flip-flop first 1 output to the first input of said first AND gate; second means connecting said second counter second 1 output to said second AND gate first input, said logic circuit being constructed to cause said counter first flip-flop to produce pulses at the 1 output thereof at a pulse repetition frequency f, said logic circuit being constructed to cause said counter second flip-flop to produce pulses at the 1 output thereof at a pulse repetition frequency of f/2; a storage register having at least first and second flip-flops corresponding to the most and next most significant digits, respectively, contained in said register; means to change the states of said register flip-flops in accordance with a function of a predetermined variable, said first and second register flip-flops each having a respective 1 output connected to the second inputs of said first and second AND gates, respectively; and an OR gate having first and second inputs connected from the outputs of said first and second AND gates, respectively, said first and second AND gates causing first and second sets of pulses, respectively, to be impressed on said OR gate first and second inputs, respectively, each of the pulses in said first set occurring at a time different from all those times at which the pulses of said second set occur.

Claim 12

Apparatus for generating a serial group of pulses wherein the number of pulses in a group is equal to a known variable digital number, said apparatus comprising: a binary digital pulse counter including a logic circuit and at least first and second flip-flops connected therefrom; means to supply input pulses to said logic circuit at a pulse repetition frequency 2f; at least first and second AND gates each having first and second inputs and an output, said counter first and second flip-flops having first and sEcond 1 outputs, respectively, first means connecting said first counter flip-flop first 1 output to the first input of said first AND gate; second means connecting said second counter second 1 output to said second AND gate first input, said logic circuit being constructed to cause said counter first flip-flop to produce pulses at the 1 output thereof at a pulse repetition frequency f, said logic circuit being constructed to cause said counter second flip-flop to produce pulses at the 1 output thereof at a pulse repetition frequency of f/2; a storage register having at least first and second flip-flops corresponding to the most and next most significant digits, respectively, contained in said register; means to change the states of said register flip-flops in accordance with a function of a predetermined variable, said first and second register flip-flops each having a respective 1 output connected to the second inputs of said first and second AND gates, respectively; and an OR gate having first and second inputs connected from the outputs of said first and second AND gates, respectively, said first and second AND gates causing first and second sets of pulses, respectively, to be impressed on said OR gate first and second inputs, respectively, each of the pulses in said first set occurring at a time different from all those times at which the pulses of said second set occur.

Claim 13

The invention as defined in claim 10, wherein said first means includes a first differentiator, said second means including a second differentiator.

Claim 14

The invention as defined in claim 11, wherein both of said AND gates are sensitive to D.C. voltages of the same polarity, both of said AND gates being insensitive to all D.C. voltages of a polarity opposite said same polarity.

Claim 15

The invention as defined in claim 10, wherein both of said AND gates are sensitive to D.C. voltages of the same polarity, both of said AND gates being insensitive to all D.C. voltages of a polarity opposite said same polarity.

Claim 16

A pulse train modification circuit comprising: first means to supply input pulses, each of said input pulses having a lead edge and a trailing edge; an OR gate; an inverter having an input junction connected from said first means and an output junction; second means connected from one of said junctions to said OR gate to supply pulses to said OR gate approximately on the occurrence of the same one edge of at least a portion of said input pulses; a flip-flop having a set input, a reset input, and a 0 output; third means connected from at least one of said junctions and actuable to supply pulses to said set input at times different from the times at which both of said leading and trailing edges occur; fourth means connected from the other of said junctions to supply pulses to said reset input at approximately the same time that the same predetermined edge of each input pulse occurs, said predetermined edge being different from the said same one edge; and a differentiator connected from said 0 output to said OR gate.

Claim 17

A pulse train modification circuit comprising: first means to supply input pulses, each of said input pulses having a lead edge and a trailing edge; an OR gate; an inverter having an input junction connected from said first means and an output junction; second means connected from one of said junctions to said OR gate to supply pulses to said OR gate approximately on the occurrence of the same one edge of at least a portion of said input pulses; a flip-flop having a set input, a reset input, and a 0 output; third means connected from at least one of said junctions and actuable to supply pulses to said set input at times different from the times at which both of said leading and trailing edges occur; fourth means connected from the other of said junctions to supply pulses to said reset input at approximately the same time that the same predetermined edge of each input pulse occurs, said predetermined edge being different from the said same one edge; and a differentiator connected from said 0 output to said OR gate.

Claim 18

The invention as defined in claim 14, including utilization means connected from the output of said OR gate.

Claim 19

The invention as defined in claim 15, wherein said first means includes a turbine flowmeter, said utilization means including a digital pulse counter connected from the output of said OR gate, and an indicator connected from said counter to indicate the magnitude of the number accumulated therein.

Claim 20

The invention as defined in claim 16, including means to supply an input to said third means to vary the ratio of the rate at which pulses are supplied to said set input and the rate at which said input pulses are supplied to said inverter input junction by said first means.

Claim 21

The invention as defined in claim 15, including means to supply an input to said third means to vary the ratio of the rate at which pulses are supplied to said set input and the rAtio at which said input pulses are supplied to said inverter input junction by said first means.

Claim 22

The invention as defined in claim 14, including means to supply an input to said third means to vary the ratio of the rate at which pulses are supplied to said set input and the rate at which said input pulses are supplied to said inverter input junction by said first means.