US3821653A
Expired / Lapsed
US
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Computer clock for memory module
Assignee: M12 Inc
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Filing: 1973-07-16
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Granted: 1974-06-28
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Expires: 1993-07-16
Abstract
Abstract A computer clock for generating a pair of separate, related computer clock signals. The clock utilizes a precision crystal oscillator, binary counter and logic circuitry for generating the desired clock signals and features a reduction in the number of required logic gates below the conventional requirements.
Inventors
- 👤 C Fretwell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:44
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/08; G; G06; G06F; G06F1/00; G06F1/04; G06F1/06; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/0307
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
251 words
A computer clock for generating a pair of clock signals and comprising: a. an oscillator for generating output pulses; b. a count by 16 binary counter having its input connected to the oscillator output and having four binary outputs representing the ones place, the twos place, the fours place and the eights place, said counter having an input for reset to 0, said eights place output providing one of said clock signals; c. a first logic gate means having its inputs connected to said fours place output and said eights place output and its output connected to said reset input of said counter for resetting said counter after every 12 oscillator output pulses; d. a flip-flop having set and reset inputs and having an output providing the other of said clock signals; e. a second logic gate means having its output connected to the reset input of said flip-flop and having a pair of inputs connected to said ones place output and said fours place output of said counter for resetting said flip-flop to a 0 state subsequent to the fifth oscillator output pulse after the counter is reset to zero; and f. a third logic gate means having at least three inputs connected respectively to said twos place output, said fours place output and said eights place output and having its output connected to the set input of said flip-flop for setting the flip-flOp to a one state subsequent to the second oscillator output pulse after the counter is reset.
Claim 2
Dependent Claim
251 words
A computer clock for generating a pair of clock signals and comprising: a. an oscillator for generating output pulses; b. a count by 16 binary counter having its input connected to the oscillator output and having four binary outputs representing the ones place, the twos place, the fours place and the eights place, said counter having an input for reset to 0, said eights place output providing one of said clock signals; c. a first logic gate means having its inputs connected to said fours place output and said eights place output and its output connected to said reset input of said counter for resetting said counter after every 12 oscillator output pulses; d. a flip-flop having set and reset inputs and having an output providing the other of said clock signals; e. a second logic gate means having its output connected to the reset input of said flip-flop and having a pair of inputs connected to said ones place output and said fours place output of said counter for resetting said flip-flop to a 0 state subsequent to the fifth oscillator output pulse after the counter is reset to zero; and f. a third logic gate means having at least three inputs connected respectively to said twos place output, said fours place output and said eights place output and having its output connected to the set input of said flip-flop for setting the flip-flOp to a one state subsequent to the second oscillator output pulse after the counter is reset.
Claim 3
Dependent Claim
32 words
A computer clock according to claim 1 wherein said first logic gate means comprises a first nand gate and wherein said counter is reset by a 0 state at its reset input.
Claim 4
Dependent Claim
18 words
A computer clock according to claim 1 wherein said flip-flop comprises a pair of flip-flop connected nand gates.
Claim 5
Dependent Claim
17 words
A computer clock according to claim 3 wherein said second logic gate means comprises a nand gate.
Claim 6
Dependent Claim
99 words
A computer clock according to claim 3 wherein said third logic gate comprises a fourth nand gate having its output connected to said set input of said flip-flop and a pair of inverters having their outputs connected to a different one of two of the inputs of said fourth nand gate; wherein the inputs of said inverters are connected one to the fours place output of said counter and the other to the eights place output of said counter and wherein a third input of said fourth nand gate is connected to the twos place output of said counter.
Claim 7
Dependent Claim
45 words
A computer clock according to claim 5 wherein said first logic gate means comprises a first nand gate and wherein said counter is reset by application of a 0 state at its reset input and wherein said second logic gate means comprises a nand gate.
Claim 8
Dependent Claim
15 words
A computer clock according to claim 6 wherein said oscillator provides 5 MHz output pulses.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-27 | 1977-12-27 | 1978-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-27 | 1981-12-27 | 1982-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-27 | 1985-12-27 | 1986-06-28 | $7700.00 | Window Closed / Lapsed |