US3820126A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrical systems for controlling camera shutters
Assignee: Pentax Corp
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Filing: 1972-12-15
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Granted: 1974-06-25
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Expires: 1992-12-15
Abstract
Abstract An electrical system for controlling a camera shutter. The electrical system includes a memory capacitor charged according to such information as light intensity, diaphragm, aperture, and film speed. This memory capacitor is electrically connected with a timing capacitor to bias the latter, and the timing capacitor forms part of a logarithmic expansion circuit and is initially charged by a constant voltage power source circuit. The timing capacitor is discharged simultaneously with the opening of the camera shutter and an FET is electrically connected through the memory capacitor to the timing capacitor to be operated thereby, this FET being electrically connected to a trigger circuit for triggering the latter to control the operation of an electromagnet which in response to triggering of the trigger circuit brings about closing of the shutter. A control is provided for controlling the operation of at least one of the above circuits. Thus, in the case of the supply circuit for the timing capacitor and the trigger circuit the control will compensate for temperature fluctuation while in the case of the logarithmic expansion circuit the control will provide a linear discharge characteristic for the timing capacitor even though the discharge circuit for the latter includes an element such as a diode which has a non-linear characteristic.
Inventors
- 👤 Y Haratake
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:54
CPC Classifications
G; G03; G03B; G03B7/00; G03B7/08; G03B7/081; G03B7/083; G03B9/00; G03B9/58
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
274 words
In an electrical system for controlling a camera shutter, memory capacitor means and signal-generating means electrically connected to said memory capacitor means for charging the latter according to an information signal determined by factors such as light intensity, diaphragm aperture, and film speed, timing capacitor means forming part of a logarithmic expansion circuit means and electrically connected with said memory capacitor means to be biased thereby, constant voltage power source circuit means electrically connected with said timing capacitor means for charging the latter with a constant voltage, switch means electrically connected with said timing capacitor means for commencing the discharge thereof simultaneously with the opening of a camera shutter, capacItor-controlled means electrically connected through said memory capacitor means with said timing capacitor means to be controlled by the discharge of said timing capacitor means as biased by said memory capacitor means, trigger circuit means electrically connected with said capacitorcontrolled means to be triggered thereby, electromagnet means for determining the instant when the camera shutter closes, electrical means connected between said electromagnet means and said trigger circuit means for operating said electromagnet means to terminate the opening of the shutter in response to triggering of said trigger circuit means by said capacitor-controlled means, said logarithmic expansion circuit means including a diode and a variable resistor connected in series with each other, said diode and variable resistor being connected in parallel with said timing capacitor means across the latter to form a discharge circuit therefor, and said variable resistor being adjusted to provide a linear discharge characteristic for the discharge circuit of said timing capacitor means by operating essentially in the range of high shutter speeds.
Claim 2
Dependent Claim
274 words
In an electrical system for controlling a camera shutter, memory capacitor means and signal-generating means electrically connected to said memory capacitor means for charging the latter according to an information signal determined by factors such as light intensity, diaphragm aperture, and film speed, timing capacitor means forming part of a logarithmic expansion circuit means and electrically connected with said memory capacitor means to be biased thereby, constant voltage power source circuit means electrically connected with said timing capacitor means for charging the latter with a constant voltage, switch means electrically connected with said timing capacitor means for commencing the discharge thereof simultaneously with the opening of a camera shutter, capacItor-controlled means electrically connected through said memory capacitor means with said timing capacitor means to be controlled by the discharge of said timing capacitor means as biased by said memory capacitor means, trigger circuit means electrically connected with said capacitorcontrolled means to be triggered thereby, electromagnet means for determining the instant when the camera shutter closes, electrical means connected between said electromagnet means and said trigger circuit means for operating said electromagnet means to terminate the opening of the shutter in response to triggering of said trigger circuit means by said capacitor-controlled means, said logarithmic expansion circuit means including a diode and a variable resistor connected in series with each other, said diode and variable resistor being connected in parallel with said timing capacitor means across the latter to form a discharge circuit therefor, and said variable resistor being adjusted to provide a linear discharge characteristic for the discharge circuit of said timing capacitor means by operating essentially in the range of high shutter speeds.
Claim 3
Dependent Claim
16 words
The combination of claim 1 and further including control means electrically connected with said trigger means.
Claim 4
Dependent Claim
46 words
The combination of claim 2 and wherein said trigger circuit means includes a pair of transistors of different polarities electrically connected to each other, said control means including a third transistor electrically connected with one of said pair of transistors and forming a voltage comparison circuit.
Claim 5
Dependent Claim
26 words
The combination of claim 3 and wherein said third transistor has the same characterisitcs as one of said pair of transistors for compensating for temperature variations.
Claim 6
Dependent Claim
97 words
The combinations of claim 3 and wherein said one transistor and said third transistor respectively have emitters electrically connected to each other, an emitter resistance electrically connected to a junction between said emitters, and a variable resistor connected to the base of said third transistor for controlling the current between the collector and emitter thereof, so that said variable resistor can adjust said third transistor for determining the operation of said trigger circuit means and for providing for said third transistor characteristics which are the same as that of said one transistor for compensating for temperature variations.
Claim 7
Dependent Claim
20 words
The combination of claim 1 and further including control means electrically connected with said constant voltage power source circuit means.
Claim 8
Dependent Claim
64 words
The combination of claim 6 and wherein said control means is a diode connected into said constant voltage power source circuit means, said diode in said logarithmic expansion circuit means and said diode in said control means having equivalent temperature characteristics so that the voltage supplied by said constant voltage power source circuit means to said timing capacitor means is compensated for temperature variations.
Claim 9
Dependent Claim
40 words
The combination of claim 1 and wherein said capacitor-controlled means is an FET having an input gate electrically connected through said memory capacitor means to said timing capacitor means and having an output electrically connected to said trigger circuit means.
Claim 10
Dependent Claim
24 words
The combination of claim 8 and wherein said signal-generating means is electrically connected to a junction between said FET and said memory capacitor means.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-24 | 1977-12-24 | 1978-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-24 | 1981-12-24 | 1982-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-24 | 1985-12-24 | 1986-06-25 | $7700.00 | Window Closed / Lapsed |