US3820111A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog-to-digital converter
Assignee: AT&T Inc
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Filing: 1972-11-13
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Granted: 1974-06-25
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Expires: 1992-11-13
Abstract
Abstract An analog signal to be converted is coupled to one input of a subtraction circuit, a second input of which is connected to receive the analog equivalent of a previously established digital word. The output of the subtraction circuit is directly connected to an integrator, the potential in which is connected to the input of a threshold classifier circuit. The classifier circuit generates an output in response to each clock pulse from a clock generator, and this output is coupled both to the above-mentioned second input of the subtraction circuit and to the input of a binary converter. The digital words formed by the binary converter are coupled to the input of a digital averaging circuit, the output of which provides the output digital word. Where the threshold classifier establishes M voltage ranges for the input analog signal, averaging of N digital words from the binary converter provides an output digital word whose accuracy is equivalent to N times M quantization levels.
Inventors
- 👤 J Candy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:02
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/30; H03M3/39; H03M3/412; H03M3/422; H03M3/424
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
412 words
An analog-to-digital converter for transforming an input analog signal into an output digital word comprising a clock generator means, quantizing means responsive to said clock generator means for converting a potential at its input into a coarsely quantized digital word and an analog value equal in magnitude to said quantized digital word, a capacitor means having a resistor and a capacitor connected in series between ground potential and a high side of said capacitor means, means for changing the potential across said capacitor means with a current which is proportional to the difference between said input analog signal and said analog value, means for coupling the potential across said capacitor means to the input of said quantizing means, and means for averaging a plurality of coarsely quantized digital words to develop said output digital word; said quantizing means for converting a potential at its input includes a classifier circuit which indicates the magnitude of said potential by energizing an appropriate number of its output terminals, and a binary converter for transforming the quantity represented by the output terminals of said classifier circuit into a binary digital word; said quantizing means further includes a plurality of resistors each one of which is connected between a different one of said output terminals and a point common to all of said plurality of resistors; and said means for changing the potential across said capacitor means includes a first and second transistor each having base, emitter and collector electrodes, said first transistor having its emitter electrode directly connected to the common point of said plurality of resistors, first resistor means for coupling said input analog signal to the emitter electrode of said first transistor, second resistor means for connecting the emitter electrode of said first transistor to a negative potential source, a diode having its anode connected to the base electrode of said first transistor and its cathode connected to ground potential, means for directly connecting the collector electrode of said first transistor to the collector electrode of said second transistor and to the high side of said capacitor means, means for forward biasing said diode from a first positive potential source, means for directly connecting the base electrode of said second transistor to said first positive poTential source, and means connected to the emitter electrode of said second transistor for forward biasing the base-emitter junction of said second transistor from a second positive potential source having a higher potential than said first positive potential source.
Claim 2
Dependent Claim
412 words
An analog-to-digital converter for transforming an input analog signal into an output digital word comprising a clock generator means, quantizing means responsive to said clock generator means for converting a potential at its input into a coarsely quantized digital word and an analog value equal in magnitude to said quantized digital word, a capacitor means having a resistor and a capacitor connected in series between ground potential and a high side of said capacitor means, means for changing the potential across said capacitor means with a current which is proportional to the difference between said input analog signal and said analog value, means for coupling the potential across said capacitor means to the input of said quantizing means, and means for averaging a plurality of coarsely quantized digital words to develop said output digital word; said quantizing means for converting a potential at its input includes a classifier circuit which indicates the magnitude of said potential by energizing an appropriate number of its output terminals, and a binary converter for transforming the quantity represented by the output terminals of said classifier circuit into a binary digital word; said quantizing means further includes a plurality of resistors each one of which is connected between a different one of said output terminals and a point common to all of said plurality of resistors; and said means for changing the potential across said capacitor means includes a first and second transistor each having base, emitter and collector electrodes, said first transistor having its emitter electrode directly connected to the common point of said plurality of resistors, first resistor means for coupling said input analog signal to the emitter electrode of said first transistor, second resistor means for connecting the emitter electrode of said first transistor to a negative potential source, a diode having its anode connected to the base electrode of said first transistor and its cathode connected to ground potential, means for directly connecting the collector electrode of said first transistor to the collector electrode of said second transistor and to the high side of said capacitor means, means for forward biasing said diode from a first positive potential source, means for directly connecting the base electrode of said second transistor to said first positive poTential source, and means connected to the emitter electrode of said second transistor for forward biasing the base-emitter junction of said second transistor from a second positive potential source having a higher potential than said first positive potential source.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-24 | 1977-12-24 | 1978-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-24 | 1981-12-24 | 1982-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-24 | 1985-12-24 | 1986-06-25 | $7700.00 | Window Closed / Lapsed |