Communication switching system having separate register subsystem and stored program processor each having its own memory,and data transfer by processor access to the register memory

Claim 1

In a communication switching system comprising common control apparatus and a switching network with markers for control thereof, in which the common control apparatus comprises a register-sender subsystem and a stored program data processing unit; wherein the register subsystem comprises a plurality of register junctors, a register memory which has junctor memory areas individual to the register junctors a common logic unit, said common logic unit including a timing generator which supplies cyclically recurring time slot signals, and time division multiplex means effectively coupling the register junctors and their individual memory areas to the common logic during their time slots for receiving, storing and other processing of call digit information, with the address for reading and writing into the register memory derived from the time slot signals, whereby the register subsystem access to the register memory is on a sequential access basis; wherein the data processing unit comprises a computer central processor and a main memory; in which the computer central processor comprises a plurality of registers including an instruction register and an accumulator register, bus means, control means, source gating means coupling outputs of the registers and the output of a main memory to the bus means, sink gating means coupling the bus means to inputs of the registers and to the main memorys and address means; wherein the main memory stores program words and data words, the program words having a format including operation code bit positions and operand bit positions, means to read program words into the instruction register, means to decode the operation code bit positions of the instruction register to supply operation codes to the control means to execute an operation specified by the operation code, which for some operation codes includes deriving an address from the operand bit positions of the instruction register to read or write data words in the main memory; register memory control apparatus in the register subsystem with means coupling the timing generator and common logic unit to the register memory, the output of the register memory beinG coupled to the common logic unit; means coupling said bus means via address conductors to the register memory control apparatus, via register subsystem sink gating means and data conductors to the register memory control apparatus, and means coupling said outputs of the register memory via register subsystem source gating means to the bus means; wherein said operation codes include a read register memory instruction and a write register memory instruction; means responsive to either a read register memory or a write register memory instruction decoded from the instruction register to gate an address derived from the operand to the register memory via the register memory control apparatus to select the address in the register memory; means further responsive to a read register memory instruction to supply a signal via the register memory control apparatus to read from the register memory, and to gate data from the register memory output via the register subsystem source gating means and the bus means to the accumulator register; and means further responsive to a write register memory instruction to supply a signal via the register memory control apparatus to write in the register memory, while gating data from the accumulator register via the bus means and the sink gating means to the register memory, thereby providing the computer central processor with random access to the register memory.