Pulse sampling and synchronization circuit

Claim 1

A pulse sampling and synchronization circuit for sampling input binary data, comprising: transition detection means for detecting transitions of the input binary data and operative to produce an output signal corresponding to each transition of the input binary data; first and second control means coupled to the transition detection means and each having an output, each of said first and second control means being operative in the absence of an output signal produced by the transition detection means to produce a first output condition at the output thereof; a source of clock pulses; counter means coupled to the outputs of the first and second control means and to the source of clock pulses and comprising: a plurality of flip-flops each having first and second inputs, a clock input, and first and second outputs, each of said flipflops having a first operating state during which a first output condition is produced at its first output and a second output condition is produced at its second output and a second operating state during which the opposite output conditions are produced at its first and second outputs; first circuit means coupled to the source of clock pulses, to the output of the first control means, and to the clock inputs of the flip-flops; second circuit means coupled between selected outputs of the flip-flops and the first and second inputs of the flip-flops and to the output of the second control means; said first and second circuit means being jointly operative when first output conditions are produced concurrently at the outputs of the first and second control means in the absence of an output signal produced by the transition detection means to establish a recurring sequence of different combinations of output conditions at predetermined outputs of the flip-flops, said different combinations of output conditions representing different operating states of the counter means; and feedback circuit means coupled between selected outputs of the flip-flops and the first and second inputs of the flip-flops and to the output of the second control means; first state-detecting means coupled to the counter means for detecting a first set of operating states of the counter means, said first state-detecting means being operative when the output conditions at the predetermined outputs of the flipflops represent the first set of operating states of the counter means to produce and output sampling signal to be used for sampling the input binary data; second state-detecting means coupled to the counter means for detecting a second set of operating states of the counter means, said second state-detecting means being operative when the output conditions at the predetermined outputs of the flipflops represent any one of the second set of operating states to produce an output signal; said first control means being further operative in response to an output signal being produced by the second state-detecting means while an output signal is produced by the transition detection means to produce a second output condition at the output thereof; said first circuit means of the counter means being further operative in response to a second output condition being produced at the output of the first control means and when a clock pulse is produced by the source of clock pulses to cause the flip-flops to produce a combination of output conditions at the predetermined outputs thereof bearing a predetermined first relationship to the then existing combination of output conditions; third state-detecting means coupled to the counter means for detecting a third set of operating states of the counter means, said third state-detecting means being operative when the output conditions at the predetermined outputs of the flipflops represent any one of the third set of operating states to produce an output signal; said second control means being further operative in response to an output signal being produced by the thrid state-detecting means while an output signal is produced by the transition detection means to produce a second output condition at the output thereof; said feedback circuit means of the counter means being operative in response to a second output condition being produced at the output of the second control means and when a clock pulse is produced by the source of clock pulses to cause the flip-flops to produce a combination of output conditions at the predetermined outputs thereof bearing a predetermined second relationship to the then existing combination of output conditions; fourth state-detecting means coupled to the counter means for detecting another state of the counter means, said fourth state-detecting means being operative when the output conditions at the predetermined outputs of the flip-flops represent said another state of the counter means to produce an output signal; said first and second control means being operative in response to an output signal being produced by the fourth statedetecting means while an output signal is produced by the transition detection means to produce first output conditions at the outputs thereof, whereby when said first state-detecting means operates to produce an output sampling signal during the first set of operating states of the counter means the leading edge of the output sampling signal bears a predetermined time relationship with respect to a particular point of a bit of the input binary data.