US3819869A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Line concentrator for telephone exchange
Assignee: Italtel SpA
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Filing: 1973-04-26
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Granted: 1974-06-25
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Expires: 1993-04-26
Abstract
Abstract A set of s incoming two-wire lines, upon carrying multifrequency digital signals from a pushbutton-type station selector, are connectable to a reduced number of n outgoing two-wire lines, leading to respective digit decoders, by means of an analog coupler comprising s input transformers and n output transformers interconnected via a common pair of bus bars which are grounded trough respective resistors. The secondaries of the input transformers and the primaries of the output transformers are connected to these bus bars through diodes normally blocking signal transmission, any of these transformers being made operative through a d-c biasing voltage applied to centertaps of the s input secondaries from a decoding matrix and to centertaps of the n output primaries from a scanner which cyclically connects that matrix to a set of n registers to sample same for the addresses of active incoming lines stored therein under the control of another scanner. The registers so sampled are loaded with the called-number digits from active lines after decoding in the signal receivers to which the digital signals are transmitted through the analog coupler.
Inventors
- 👤 A Lamartina
- 👤 A Antonini
- 👤 E Cicognani
- 👤 R Caldarella
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:12
CPC Classifications
H; H04; H04Q; H04Q3/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
336 words
In a telecommunication system including a larger multiplicity of incoming lines, a smaller multiplicity of outgoing lines and detector means connected to said incoming lines for ascertaining a signaling condition thereon, the combination therewith of: counting means for periodically generating an address of any one of said incoming lines in a predetermined order of succession; circuit means connected to said detector means for carrying activity signals identifying any of said incoming lines in the presence of said signaling condition thereon; a set of n registers with signal-storage means respectively accessible to said outgoing lines and with address-storage means having normally blocked input connections extending from said counting means; allocation means connected to said circuit means and to said counting means for receiving said addresses and said activity signals therefrom, said allocation means having n outputs for unblocking the input connection of the address-storage means oF any one of said n registers upon coincidence of an activity signal with the address of a line identified thereby; a set of first control leads with a normal and an off-normal state of energization; a set of second control leads with a normal and an off-normal state of energization; scanning means connected to said registers for periodically sampling the contents of their address-storage means and changing the state of energization of respective first control leads identifying said registers; decoding means periodically connectable to the address-storage means of all said registers under the control of said scanning means for changing the state of energization of respective second control leads identifying the active incoming lines whose addresses are stored therein; and an analog coupler inserted between said incoming and outgoing lines with a set of n inputs respectively connected to said first control leads and with a set of s inputs respectively connected to said second control leads for selectively connecting any incoming line identified by a second control lead in its off-normal state of energization with an outgoing line identified by a first control lead in an off-normal state of energization.
Claim 2
Dependent Claim
336 words
In a telecommunication system including a larger multiplicity of incoming lines, a smaller multiplicity of outgoing lines and detector means connected to said incoming lines for ascertaining a signaling condition thereon, the combination therewith of: counting means for periodically generating an address of any one of said incoming lines in a predetermined order of succession; circuit means connected to said detector means for carrying activity signals identifying any of said incoming lines in the presence of said signaling condition thereon; a set of n registers with signal-storage means respectively accessible to said outgoing lines and with address-storage means having normally blocked input connections extending from said counting means; allocation means connected to said circuit means and to said counting means for receiving said addresses and said activity signals therefrom, said allocation means having n outputs for unblocking the input connection of the address-storage means oF any one of said n registers upon coincidence of an activity signal with the address of a line identified thereby; a set of first control leads with a normal and an off-normal state of energization; a set of second control leads with a normal and an off-normal state of energization; scanning means connected to said registers for periodically sampling the contents of their address-storage means and changing the state of energization of respective first control leads identifying said registers; decoding means periodically connectable to the address-storage means of all said registers under the control of said scanning means for changing the state of energization of respective second control leads identifying the active incoming lines whose addresses are stored therein; and an analog coupler inserted between said incoming and outgoing lines with a set of n inputs respectively connected to said first control leads and with a set of s inputs respectively connected to said second control leads for selectively connecting any incoming line identified by a second control lead in its off-normal state of energization with an outgoing line identified by a first control lead in an off-normal state of energization.
Claim 3
Dependent Claim
45 words
The combination defined in claim 1, further comprising inhibiting means responsive to the entry of a stored address in any of said registers for preventing the transmission to said allocation means of an activity signal pertaining to an incoming line identified by such stored address.
Claim 4
Dependent Claim
25 words
The combination defined in claim 2 wherein said circuit means includes a set of s memory stages with read-out circuits controlled by said inhibiting means.
Claim 5
Dependent Claim
23 words
The combination defined in claim 3 wherein said inhibiting means comprises respective clearing connections between said second control leads and said memory stages.
Claim 6
Dependent Claim
73 words
The combination defined in claim 2 wherein said inhibiting means comprises a circulating memory synchronized with said counting means and connected to said n outputs for entry of bits in respective time slots assigned to active incoming lines, said allocation means having a cancellation output terminating at said circulating memory for deleting a bit stored in any of said time slots upon the disappearance of an activity signal from the corresponding incoming line.
Claim 7
Dependent Claim
158 words
The combination defined in claim 1 wherein said analog coupler comprises a group of s input transformers respectively connected to said incoming lines for energization thereby, a group of n output transformers respecitvely connected to said outgoing lines for energizing same, a pair of bus bars common to all said transformers, said output transformers having primary windings connected in parallel across said bus bars by way of respective first diode pairs, said input transformers having secondary windings connected in parallel across said bus bars by way of respective second diode pairs, the diodes of each pair being connected in bucking relationship with each other, said first control leads terminating at respective centertaps of said primary windings, said second control leads terminating at resptective centertaps of said secondary windings, and biasing means connected to said bus bars for maintaining each pair of said diodes nonconductive in the normal state of energization of the lead connected to the associated centertap.
Claim 8
Dependent Claim
21 words
The combination defined in claim 6 wherein said biasing means includes a resistive ground connection for each of said bus bars.
Claim 9
Dependent Claim
233 words
In a signaling system including a multiplicity of s incoming lines and a multiplicity of n outgoing lines, the combination therewith of an analog coupler comprising: a group of s input transformers respectively connected to said incoming lines for energization thereby; a group of n output transformers respectively connected to said outgoing lines for energizing same; a pair of bus bars common to all said transformers, said input transformers haviNg secondary windings connected in parallel across said bus bars, said output transformers having primary windings connected in parallel across said bus bars; a first diode pair connected in bucking relationship between each of said primary windings and said bus bars; a second diode pair connected in bucking relationship between each of said secondary windings and said bus bars; biasing means connecting said bus bars to a source of reference voltage; first circuit means normally applying a blocking voltage to each first diode pair, said first circuit means being selectively switchable to apply an unblocking voltage to any one of said first diode pairs; and second circuit means normally applying a blocking voltage to each second diode pair, said second circuit means being selectively switchable to apply an unblocking voltage to any one of said second diode pairs whereby signals from an input transformer associated with an unblocked second diode pair are transmitted to an output transformer associated with an unblocked first diode pair.
Claim 10
Dependent Claim
233 words
In a signaling system including a multiplicity of s incoming lines and a multiplicity of n outgoing lines, the combination therewith of an analog coupler comprising: a group of s input transformers respectively connected to said incoming lines for energization thereby; a group of n output transformers respectively connected to said outgoing lines for energizing same; a pair of bus bars common to all said transformers, said input transformers haviNg secondary windings connected in parallel across said bus bars, said output transformers having primary windings connected in parallel across said bus bars; a first diode pair connected in bucking relationship between each of said primary windings and said bus bars; a second diode pair connected in bucking relationship between each of said secondary windings and said bus bars; biasing means connecting said bus bars to a source of reference voltage; first circuit means normally applying a blocking voltage to each first diode pair, said first circuit means being selectively switchable to apply an unblocking voltage to any one of said first diode pairs; and second circuit means normally applying a blocking voltage to each second diode pair, said second circuit means being selectively switchable to apply an unblocking voltage to any one of said second diode pairs whereby signals from an input transformer associated with an unblocked second diode pair are transmitted to an output transformer associated with an unblocked first diode pair.
Claim 11
Dependent Claim
36 words
The combination defined in claim 8 wherein the diodes of each pair are connected to opposite terminals of the associated winding, said first and second circuit means comprising leads terminating at the midpoints of said windings.
Claim 12
Dependent Claim
26 words
The combination defined in claim 8 wherein said biasing means comprises a pair of resistors inserted between said source of reference voltage and said bus bars.
References Cited (Backward Citations)
US3206553A
Cited
US3592970A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-24 | 1977-12-24 | 1978-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-24 | 1981-12-24 | 1982-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-24 | 1985-12-24 | 1986-06-25 | $7700.00 | Window Closed / Lapsed |