Auxiliary memory interface system

Claim 2

Interface apparatus for coupling an auxiliary memory containing N pages to a central processing unit having M pages of memory; said interface apparatus comprising address modification means for transferring memory addresses from the central processing unit to the auxiliary memory, said address modification means comprising subtractor means for subtracting M from the page number portion of the memory addresses during transfer to provide modified page numbers to which the auxiliary memory responds.

Claim 3

Interface apparatus according to claim 1 comprising selector means for enabling operation of the auxiliary memory in response to the receipt of a memory address corresponding to a memory location within the auxiliary memory.

Claim 4

Interface apparatus according to claim 2 wherein said selector means comprises comparator means for receiving the modified page numbers from said subtractor means and providing an activate signal in response to modified page numbers of less than N+1.

Claim 5

Interface apparatus according to claim 3 comprising synchronizing logic means for coupling the commands of the central processing unit to the auxiliary memory, said synchronizing logic means comprising delay means for inhibiting the operation of the auxiliary memory for a preselected time following the receipt of a command by said synchronizing logic means.

Claim 6

Interface apparatus according to claim 4 wherein said synchronizing logic means comprises gate means operatively coupled to said comparator means for initiating operation of the auxiliary memory following the expiration of the preselected time and receipt of the activate signal.

Claim 7

Interface apparatus according to claim 5 wherein said synchronizing logic means comprises inhibit means coupled to said gate means and the auxiliary memory for inhibiting the operation of said gate means in response to a busy signal from the auxiliary memory.

Claim 8

Interface apparatus for coupling an auxiliary memory containing N pages to a central processing unit already including pages of memory numbered up to M, said apparatus comprising: address modification means for transferring memory addresses from the central processing unit to the auxiliary memory and including: subtractor means for subtracting M from the page number portions of the memory addresses to provide modified page numbers to which the auxiliary memory responds; comparator means for providing an activate signal in response to modified page numbers of greater than zero and less than N+1; synchronizing logic means comprising: delay means for inhibiting the operation of the auxiliary memory for a preselected time following the receipt of a command by said synchronizing logic means; gate means operatively coupled to said comparator means for initiating operation of the auxiliary memory following the preselected time and receipt of the activate signal; and inhibit means for inhibiting the operation of said gate means in response to a busy signal from the auxiliary memory.

Claim 9

Interface apparatus for coupling an auxiliary memory containing N pages to a central processing unit already including pages of memory numbered up to M, said apparatus comprising: address modification means for transferring memory addresses from the central processing unit to the auxiliary memory and including: subtractor means for subtracting M from the page number portions of the memory addresses to provide modified page numbers to which the auxiliary memory responds; comparator means for providing an activate signal in response to modified page numbers of greater than zero and less than N+1; synchronizing logic means comprising: delay means for inhibiting the operation of the auxiliary memory for a preselected time following the receipt of a command by said synchronizing logic means; gate means operatively coupled to said comparator means for initiating operation of the auxiliary memory following the preselected time and receipt of the activate signal; and inhibit means for inhibiting the operation of said gate means in response to a busy signal from the auxiliary memory.

Claim 10

Interface apparatus according to claim 7 wherein said synchronizing logic means further comprises read gating Means responsive to read commands from the central processing unit and enabling signals from the auxiliary memory for coupling a data register in the auxiliary memory to the central processing unit.

Claim 11

Interface apparatus according to claim 8 wherein said read gating means comprises reset means for disconnecting the data register from the central processing unit in reponse to a data acknowledge signal from the central processing unit.

Claim 12

Interface apparatus according to claim 9 wherein said synchronizing logic means further comprises write means responsive to an enable signal from the auxiliary memory and a memory release signal from the central processing unit for setting to cause the auxiliary memory to write the contents of a data register in the auxiliary memory into a preselected memory location.

Claim 13

Interface apparatus according to claim 10 wherein said write means comprises reset means for resetting said write means.

Claim 14

Interface apparatus according to claim 11 wherein said reset means comprises automatic delay reset means for automatically resetting said write means after a predetermined set time.

Claim 15

Auxiliary memory apparatus for use in conjunction with a central processing unit already including pages of memory numbered up to M, said apparatus comprising: auxiliary memory means comprising N pages of auxiliary memory; a data register for use in conjunction with said N pages; an address register for use in conjunction with said N pages; address modification means for transferring memory addresses from the central processing unit to said address register and comprising subtractor means for subtracting M from the page number portion of the memory addresses to provide modified page numbers which are delivered to said address register; comparator means for providing an activate signal in response to modified page numbers of greater than zero and less than N+1; synchronizing logic means comprising delay means for inhibiting the operation of said auxiliary memory means for a preselected time following the receipt of a command by said synchronizing logic means; gate means operatively coupled to said comparator means for intiating operation of said auxiliary memory means following the preselected time and receipt of the activate signal; and inhibit means for inhibiting the operation of said gate means in response to a busy signal from said auxiliary memory means.

Claim 16

Auxiliary memory apparatus for use in conjunction with a central processing unit already including pages of memory numbered up to M, said apparatus comprising: auxiliary memory means comprising N pages of auxiliary memory; a data register for use in conjunction with said N pages; an address register for use in conjunction with said N pages; address modification means for transferring memory addresses from the central processing unit to said address register and comprising subtractor means for subtracting M from the page number portion of the memory addresses to provide modified page numbers which are delivered to said address register; comparator means for providing an activate signal in response to modified page numbers of greater than zero and less than N+1; synchronizing logic means comprising delay means for inhibiting the operation of said auxiliary memory means for a preselected time following the receipt of a command by said synchronizing logic means; gate means operatively coupled to said comparator means for intiating operation of said auxiliary memory means following the preselected time and receipt of the activate signal; and inhibit means for inhibiting the operation of said gate means in response to a busy signal from said auxiliary memory means.

Claim 17

Auxiliary memory apparatus according to claim 13 wherein said synchronizing logic means further comprises read gating means responsive to read commands from the central processing unit and enabling signals from said auxiliary memory means for coupling said data register to the central processing unit.

Claim 18

Auxiliary memory apparatus according to claim 14 wherein said read gating means comprises reset means for disconnecting said data register from the central processing unit in response to a data acknowledge signal from the central processing unit.

Claim 19

Auxiliary memory apparatus according to claim 15 wherein said synchronizing logic means further comprises write means responsive to an enable signal from said auxiliary memory means and a memory release signal from the central processing unit for setting to cause said auxiliary memory means to write the contents of said data bus and data register into the preselected memory location.

Claim 20

Auxiliary memory apparatus according to claim 16 wherein said write means comprises reset means for resetting said write means.

Claim 21

Auxiliary memory apparatus according to claim 17 wherein said reset means comprises automatic delay reset means for automatically resetting said write means after a preselected set time.

Claim 22

Auxiliary memory apparatus according to claim 18 wherein N is greater than one.

Claim 23

Interface apparatus for coupling an auxiliary memory containing N pages to a central processing unit already including pages of memory numbered up to M, said apparatus comprIsing: address modification means for transferring memory addresses from the central processing unit to the auxiliary memory and including; means for determining whether the page number portions of the memory addresses exceed M for providing an activate signal in response to modified page numbers of greater than zero and less than N+1 and providing modified page numbers to which the auxiliary memory responds; comparator means and synchronizing logic means for enabling operation of the auxiliary memory following the receipt of the activate signal.

Claim 24

Interface apparatus for coupling an auxiliary memory containing N pages to a central processing unit already including pages of memory numbered up to M, said apparatus comprIsing: address modification means for transferring memory addresses from the central processing unit to the auxiliary memory and including; means for determining whether the page number portions of the memory addresses exceed M for providing an activate signal in response to modified page numbers of greater than zero and less than N+1 and providing modified page numbers to which the auxiliary memory responds; comparator means and synchronizing logic means for enabling operation of the auxiliary memory following the receipt of the activate signal.