US3817023A
Expired / Lapsed
US
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Clock devices
Assignee: Casio Computer Co Ltd
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Filing: 1973-04-11
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Granted: 1974-06-18
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Expires: 1993-04-11
Abstract
Abstract In a clock device wherein hours and minutes are displayed by a driving circuit including a ''''second'''' counter, a ''''minute'''' counter, and an ''''hour'''' counter, there is provided a correction key which provides a first signal for stopping the counting operation and clearing the content of the ''''second'''' counter and for stepping one step the content of the ''''minute'''' counter when the key is operated, and a second signal for causing the cleared ''''second'''' counter to commence the counting operation of seconds.
Inventors
- 👤 T Kashio
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:33
CPC Classifications
G; G04; G04G; G04G5/00; G04G5/04; G04G5/02
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
140 words
A clock device comprising: a source of signals having a stable frequency; a ''''second'''' counter to count signals from said signal source and for generating ''''1 minute'''' stepping signals at a rate of one per 60 seconds; a ''''minute'''' counter to count said ''''1 minute'''' stepping signals and for generating ''''1 hour'''' stepping signals at a rate of one per 60 minutes; an ''''hour'''' counter for counting said ''''1 hour'''' counting signals; and means coupled to said signal source, said ''''second'''' counter, and said ''''minute'''' counter for generating a first signal for stopping the counting operation and clearing the content of said ''''second'''' counter and for stepping by one step the content of said ''''minute'''' counter and for generating a second signal for causing said cleared ''''second'''' counter to commence a counting operation of signals from the initial count thereof.
Claim 2
Dependent Claim
140 words
A clock device comprising: a source of signals having a stable frequency; a ''''second'''' counter to count signals from said signal source and for generating ''''1 minute'''' stepping signals at a rate of one per 60 seconds; a ''''minute'''' counter to count said ''''1 minute'''' stepping signals and for generating ''''1 hour'''' stepping signals at a rate of one per 60 minutes; an ''''hour'''' counter for counting said ''''1 hour'''' counting signals; and means coupled to said signal source, said ''''second'''' counter, and said ''''minute'''' counter for generating a first signal for stopping the counting operation and clearing the content of said ''''second'''' counter and for stepping by one step the content of said ''''minute'''' counter and for generating a second signal for causing said cleared ''''second'''' counter to commence a counting operation of signals from the initial count thereof.
Claim 3
Dependent Claim
43 words
A clock device according to claim 1 wherein said means for generating said first and second signals comprises a time correction key, said first signal being generated when said key is operated and said second signal being generated when said key is released.
Claim 4
Dependent Claim
138 words
A clock device comprising: a source of signals having a stable frequency; a ''''second'''' counter to count signals from said signal source and for generating ''''1 minute'''' stepping signals at a rate of one per 60 seconds; a ''''minute'''' counter to count said ''''1 minute'''' stepping signals for generating ''''1 hour'''' stepping signals at a rate of one per 60 minutes; an ''''hour'''' counter for counting said ''''1 hour'''' stepping signals; and means coupled to said signal source, said ''''second'''' counter, and said ''''minute'''' counter for generating a first signal for stopping the counting operation and clearing the content of said ''''second'''' counter and for generating a second signal for causing said cleared ''''second'''' counter to commence the counting operation of signals from the initial count thereof and advancing by one step the content of said ''''minute'''' counter.
Claim 5
Dependent Claim
138 words
A clock device comprising: a source of signals having a stable frequency; a ''''second'''' counter to count signals from said signal source and for generating ''''1 minute'''' stepping signals at a rate of one per 60 seconds; a ''''minute'''' counter to count said ''''1 minute'''' stepping signals for generating ''''1 hour'''' stepping signals at a rate of one per 60 minutes; an ''''hour'''' counter for counting said ''''1 hour'''' stepping signals; and means coupled to said signal source, said ''''second'''' counter, and said ''''minute'''' counter for generating a first signal for stopping the counting operation and clearing the content of said ''''second'''' counter and for generating a second signal for causing said cleared ''''second'''' counter to commence the counting operation of signals from the initial count thereof and advancing by one step the content of said ''''minute'''' counter.
Claim 6
Dependent Claim
43 words
A clock device according to claim 3 wherein said means for generating said first and second signals comprises a time correction key, said first signal being generated when said key is operated and said second signal being generated when said key is released.
Claim 7
Dependent Claim
50 words
A clock device according to claim 1 wherein said source of signals comprises a clock signal generating circuit for generating a standard high frequency signal; and a frequency dividing counter for reducing the frequency of said standard high frequency signal, said reduced frequency signal being counted by said ''''second'''' counter.
Claim 8
Dependent Claim
24 words
A clock device according to claim 1 wherein said first signal is coupled to said frequency dividing counter for resetting said frequency dividing counter.
Claim 9
Dependent Claim
50 words
A clock device according to claim 3 wherein said source of signals comprises a clock signal generating circuit for generating a standard high frequency signal; and a frequency dividing counter for reducing the frequency of said standard high frequency signal, said reduced frequency signal being counted by said ''''second'''' counter.
Claim 10
Dependent Claim
24 words
A clock device according to claim 3 wherein said first signal is coupled to said frequency dividing counter for resetting said frequency dividing counter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-17 | 1977-12-17 | 1978-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-17 | 1981-12-17 | 1982-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-17 | 1985-12-17 | 1986-06-18 | $7700.00 | Window Closed / Lapsed |